Changes
/* I/O Ports */
Here are the I/O Ports (same for original and Pace version):
FADCh Amstrad RS323 RS232 [[Z80-DART/Z80-SIO chip|Z8470 (Z80 DART)]] Channel A Data (R/W) FADDh Amstrad RS323 RS232 [[Z80-DART/Z80-SIO chip|Z8470 (Z80 DART)]] Channel A Control/Status (R/W) FADEh Amstrad RS323 RS232 [[Z80-DART/Z80-SIO chip|Z8470 (Z80 DART)]] Channel B Data (R/W) FADFh Amstrad RS323 RS232 [[Z80-DART/Z80-SIO chip|Z8470 (Z80 DART)]] Channel B Control/Status (R/W) FBDCh Amstrad RS323 RS232 [[8253 chip|8253]] Baudrate Timer 0 Channel A TX Clock (R/W) FBDDh Amstrad RS323 RS232 [[8253 chip|8253]] Baudrate Timer 1 Channel A RX Clock (R/W) FBDEh Amstrad RS323 RS232 [[8253 chip|8253]] Baudrate Timer 2 Channel B RX/TX Clock (R/W) FBDFh Amstrad RS323 RS232 [[8253 chip|8253]] Baudrate Timer 0-2 Control Registers (W)
Note: Some interfaces might use a Z80 SIO (which is backwards compatible to the Z80 DART).
