Changes
6502
,/* Illegal instructions */
=== Illegal instructions ===
The opcodes in bold red are unstable. Only 2 of those 7 opcodes ($8B, $AB) are actually unstable in the sense that they may produce a truly unpredictable result. The other 5 opcodes actually produce predictable results – but the conditions under which they do that and the produced results are a bit unexpected.
{| class="wikitable" style="white-space: nowrap;"
| LAS (LAR) || STA/TXS + LDA/STX || || || || || BB (4+p) || || || || || || N || - || - || - || - || - || Z || - || M ∧ S → A, X, S || "AND" Memory with Stack Pointer
|-
| LAX (LXA) || LDA + LDX || || style="color: #CC0000;"| '''AB''' (2) || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || - || - || Z || - || M → A, X || Load Accumulator and Index Register X From Memory
|-
| NOP (DOP, TOP) || || 1A, 3A, 5A,
| SBX (AXS, SAX) || CMP + DEX || || CB (2) || || || || || || || || || N || - || - || - || - || - || Z || C || (A ∧ X) - M → X || Subtract Memory from Accumulator "AND" Index Register X
|-
| SHA (AHX, AXA) || STA/STX/STY || || || || || style="color: #CC0000;"| '''9F''' (5) || || || || || style="color: #CC0000;"| '''93''' (6) || - || - || - || - || - || - || - || - || A ∧ X ∧ V → M || Store Accumulator "AND" Index Register X "AND" Value
|-
| SHS (TAS, XAS) || STA/TXS + LDA/TSX || || || || || style="color: #CC0000;"| '''9B''' (5) || || || || || || - || - || - || - || - || - || - || - || A ∧ X → S, S ∧ (H + 1) → M || Transfer Accumulator "AND" Index Register X to Stack Pointer then Store Stack Pointer "AND" Hi-Byte In Memory
|-
| SHX (SXA, XAS) || STA/STX/STY || || || || || style="color: #CC0000;"| '''9E''' (5) || || || || || || - || - || - || - || - || - || - || - || X ∧ (H + 1) → M || Store Index Register X "AND" Value
|-
| SHY (SYA, SAY) || STA/STX/STY || || || || style="color: #CC0000;"| '''9C''' (5) || || || || || || || - || - || - || - || - || - || - || - || Y ∧ (H + 1) → M || Store Index Register Y "AND" Value
|-
| SLO (ASO) || ASL + ORA || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || - || - || Z || C || M * 2 → M, A ∨ M → A || Arithmetic Shift Left then "OR" Memory with Accumulator
| SRE (LSE) || LSR + EOR || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || - || - || Z || C || M / 2 → M, A ⊻ M → A || Logical Shift Right then "Exclusive OR" Memory with Accumulator
|-
| XAA (ANE) || TXA + AND || || style="color: #CC0000;"| '''8B''' (2) || || || || || || || || || N || - || - || - || - || - || Z || - || (A ∨ V) ∧ X ∧ M → A || Non-deterministic Operation of Accumulator, Index Register X, Memory and Bus Contents
|}
