Changes
/* Video memory structure */
== Interrupt management ==
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter (R52(the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
Note: On Amstrad Plus, the Gate Array interrupt management system is not seriously beefed up. See the sole generator of interrupts. The 3 DMA sound channels are each able to trigger an interrupt. The [[ASIC also provides an interrupt vector register (IVR) for vectorized interrupts. And it offers a programmable raster interrupt register (PRI) that can be used instead of the normal raster interrupt mechanism]] wiki page.
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The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.
{|{{Prettytable|width: 700px; font-size: 2em;}}|-class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
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{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit 1'' || ''!Bit 0'' || ''!Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
== Video memory structure ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|!rowspan=2|'''Graphics Mode'''||!colspan=8 style="text-align: center;"|'''VRAM byte'''||!colspan=8 style="text-align: center;"|'''Displayed Pixels'''||!rowspan=2|'''Definition'''
|-
|-
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