Changes
CRTC
,/* DISPTMG (aka Display Enable) */
The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), IBORDER (Immediate) by using the NOR function. DISPTMG can be immediately forced to 0 by using R8 (DISPTMG Skew) on type CRTCs 0,/3 and /4 or by setting R6=0 on type CRTC 1. It is not possible to force the DISPTMG on type CRTC 2.
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On CRTCs 0/2, registers 18-31 read as 0, on type 0 and 2. On CRTC 1, registers 18-30 read as 0 on type1, register 31 reads as 0xff.
Details about Reg. 12 and Reg. 13 specifically:
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=== R31 on Type 1 Vertical Displayed (R6) ===
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=== R12/R13 R31 on Type 1 ===
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=== R10/R11 on ASIC/Pre-ASIC ===
The cursor raster registers R10/R11 act as status registers when read on Types CRTCs 3 & /4. They behave as normal cursor raster registers upon write.
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=== Reading from CRTC registers on ASIC/Pre-ASIC ===
On CRTC Types CRTCs 3 and /4, only the 3 least significant bits of the selected register number are considered to read a register according to the following table:
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No matter its type, the CRTC never buffers its counters.
The only value that is saved in a buffer in the CRTC is the video pointer MA because it is reloaded at each raster line start. R12/R13 is loaded only once per frame, in MA and MA', at the first raster line start of the frame. The counter MA is then reloaded with the value of MA' at each raster line start. And at each new character line start, MA' captures the current value of MA. The exception is the CRTC 1 for which the MA is reloaded at each raster line start with R12/R13 instead of MA' as long as C4VCC=0. This is a major source of incompatibility if the programmer does not take care of this discrepancy. In demos and games, to make a display compatible with all CRTCs, program R12/R13 when VCC!=0. This will then take effect at the next frame start.
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During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will continue to count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.
The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.
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If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping backand counting up again until it reaches the new value of R9* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC changes will reset to 0 on the next line
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=== VTAC (C5/C9) overflow ===
During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will continue to count up to its maximum value (31) before looping backand counting up again until it reaches the new value of R5* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment endswill end
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== Hitachi Block Diagram Diagrams == === Hitachi ===
[[File:CRTC Block Diagram.png]]
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=== UMC Block Diagram ===
[[File:UMC CRTC Block Diagram.png]]
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=== Motorola Block Diagram ===
[[File:Motorola CRTC Block Diagram.png]]
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=== Unused clones ===
* [[CM607P]] a Bulgarian clone made in Pravetz factory
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors
