I/O Ports
Used in standard RS232 interfaces for the CPC (Amstrad Serial Interface), mapped to following Ports:
FADCh Amstrad RS323 Z8470 (Z80 DART) Channel A Data (R/W) FADDh Amstrad RS323 Z8470 (Z80 DART) Channel A Control/Status (R/W) FADEh Amstrad RS323 Z8470 (Z80 DART) Channel B Data (R/W) FADFh Amstrad RS323 Z8470 (Z80 DART) Channel B Control/Status (R/W)
Also used by Z80-SIO dual ports RS232 interface for CPC (French), mapped to:
FC7Ch Z80 SIO Channel A Data FC7Dh Z80 SIO Channel A Control/Status FC7Eh Z80 SIO Channel B Data FC7Fh Z80 SIO Channel B Control/Status
Chip Variants (DART, SIO/0, SIO/1, SIO/2, SIO/3, SIO/4)
Most CPC interfaces should contain the DART chips. Eventually some might use the SIO chips (which are including some additional features).
- Zilog Z8470 - Z80 DART (Dual-channel Asynchronous Receiver Transmitter)
- Zilog Z8440 - Z80 SIO (Dual-channel Serial Input/Output Controller)
Note: Five different variants of the SIO chips exist: types 0/1/2 are 40pin DIP chips with slightly different features/pinouts, types 3 (QFP package) and 4 (PLCC package) are 44pin chips, both combining all features of the three 40pin chips.
Control/Status Registers
In the default state, reads/writes on the Control/Status port are accessing the RR0/WR0 registers. After writing a non-zero index value "n" to Bit0-2 of WR0, the next read/write operation on the Control/Status port will access the corresponding RRn/WRn register.
Control Registers
WR0 Write register 0
0-2 Register Index (0-5 for write, 0-2 for read) (SIO: 0-7 for write)
3-5 Command (0..7)
0=No action
1=DART: Reserved / SIO: Send Abort (SDLC)
2=Reset Ext/Status Interrupts
3=Reset Channel
4=Enable Interrupt on next Rx character
5=Reset Tx Int pending
6=Reset Error
7=Return from Int (Ch-A only)
6-7 CRC Reset Code (DART: Reserved, should be 0) (SIO: 0..3)
0=No action
1=DART: Reserved, SIO: Reset Receive CRC Checker
2=DART: Reserved, SIO: Reset Transmit CRC Generator
3=DART: Reserved, SIO: Reset Tx Underrun/End of Message latch
WR1 Write register 1
0 External Interrupts Enable
1 Tx Interrupt Enable
2 Status Affects Vector (Channel B only) (see WR2/RR2)
3-4 Rx Interrupt Mode (0..3)
0=None
1=On first Rx char
2=On all Rx chars (Parity affects vector)
3=On all Rx chars (Parity does not affect vector)
5 Wait/Ready on Receive/Transmit
6 Wait/Ready Function
7 Wait/Ready Enable
WR2 Write register 2 - Interrupt Vector (Channel B only)
0-7 Interrupt Vector (Bit1-3=no effect when WR1.Bit2=1, see RR2 for details)
WR3 Write register 3 - Rx Control
0 Rx Enable 1 DART: Reserved (must be 0), SIO: Sync Char Load Inhibit 2 DART: Reserved (must be 0), SIO: Address Search Mode 3 DART: Reserved (must be 0), SIO: Receiver CRC Enable 4 DART: Reserved (must be 0), SIO: Enter Hunt Phase 5 Enable automatic hardware handshaking using RTS/CTS 6-7 Rx data bits (0..3 = 5bits, 7bits, 6bits, 8bits)
WR4 Write register 4 - Rx/Tx Control
0 Rx/Tx Parity bit (0=None, 1=Enable)
1 Rx/Tx Parity type (0=Odd, 1=Even)
2-3 Rx/Tx Stop bits (0..3=Reserved, 1bit, 1.5bits, 2bits) (SIO: 0=Sync Modes)
4-5 DART: Reserved (must be 0), SIO: Sync Mode (enabled when Bit2-3=zero)
0=8bit SYNC Character (SIO only, not DART)
1=16bit SYNC Character (SIO only, not DART)
2=SDLC Mode (0111 1110 Flag) (SIO only, not DART)
3=External SYNC Mode (SIO only, not DART)
6-7 Rx/Tx DART clock mode (0..3=X1, X16, X32, X64)
WR5 Write register 5 - Tx Control
0 DART: Reserved (must be 0), SIO: Tx CRC Enable 1 RTS enabled/disabled 2 DART: Reserved (must be 0), SIO: Rx/Tx CRC Type (0=SDLC, 1=CRC-16) 3 Tx Enable 4 Tx Send break 6-5 Tx data bits (0..3 = 5bits, 7bits, 6bits, 8bits) 7 DTR enabled/disabled
WR6 Write register 6 - Sync Character or SDLC address (Z80 SIO only)
0-7 DART: N/A, SIO: LSBs of 8bit/16bit sync char, or SDLC address
WR7 Write register 7 - Sync Character or SDLC flag (Z80 SIO only)
0-7 DART: N/A, SIO: MSBs of 16bit sync char, or SDLC flag (should be 7Eh)
Status Registers
RR0 Read register 0 (General Status Bits)
0 Rx character available (3-stage RXFIFO not emtpy) 1 interrupt pending (Channel A only) (always 0 on Channel B) 2 Tx buffer empty (1-stage RXFIFO emtpy) 3 DCD (carrier detect) 4 DART: RI (ring indicate), SIO: Sync/Hunt 5 CTS 6 DART: Not used, SIO: Transmit Underrun/End of Message 7 break received, SIO: Break/Abort
RR1 Read register 1 (Used with Special Receive Condition Mode)
0 Tx all sent (1-stage TXFIFO and TX-shift register empty) 1-3 DART: Not used, SIO: Residue Codes 4 Rx parity error 5 Rx overrun error 6 framing error SIO: CRC or Framing Error 7 DART: Not used, SIO: End of Frame
RR2 Read register 2 (Interrupt Vector) (Channel B only)
0-7 Interrupt Vector (as set via WR2) (Bit1-3=variable when WR1.Bit2=1)
0 Channel B Transmit Buffer Empty (1-stage TXFIFO empty)
1 Channel B External/Status Change
2 Channel B Receive Character Available (3-stage RXFIFO not empty)
3 Channel B Parity/Rx Overrun/Framing Error, or End-of-Frame (SDLC)
4-7 Same as above, but for Channel A
RR3-7 Read registers 3..7 - Reserved
- Reserved / don't use
Data Registers
Rx Data Register
has a 3-stage FIFO, plus 1 rx shift register (4-stages in total)
Tx Data Register
has a 1-stage FIFO, plus 1 tx shift register (2-stages in total)
Interrupt Notes
Interrupts can occur on both channel A and channel B, certain bits (like interrupt enable flags) can be configured separately for each channel, other bits are shared for both channels: the interrupt vector can be accessed via RR2/WR2 of channel B only the interrupt pending flag can be read via RR0.Bit1 of channel A only
The DART/SIO interrupt signal is known to be connected to the CPC hardware on the original Amstrad CPC serial interface. It is unknown if this is the case on the later revision or 3rd party interfaces.
Usage of native Z80 peripheral interrupts is complicated by their knowledge of CPU interrupt acknowledge signals which conflict with the Gate Array interrupts. A workaround is documented in the firmware guide appendix 13.