You can also have local registered value, using affectation operator ":=", without delta-time (at once) :
output_write_mem output_wire_mem := input_write input_wire xor 1; output_write_mem output_wire_mem := output_write_mem output_wire_mem xor 1; output_write output_wire <= output_write_memoutput_wire_mem;
VHDL can be synthetised (compiled) into FPGA chip. Two families of FPGA chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...