The SRAM/Write mode doesn't disable the internal RAM in the CPC, so writes are going both to SRAM and normal RAM at C000-FFFF, that no matter if upper ROM is enabled/disabled via Gate Array; the author recommended to map VRAM to 4000-7FFF via CRTC registers, in order to prevent video dirt during writing.
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|F8E0h || F8F0h (later redefined to F8E4h) || Schneiderware Centronics 8255 PPI Port A (data)
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|F8E1h || F8F1h (later redefined to F8E5h) || Schneiderware Centronics 8255 PPI Port B (unused)
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|F8E2h || F8F2h (later redefined to F8E6h) || Schneiderware Centronics 8255 PPI Port C (busy/strobe)<br>(bit7=busy, bit6-1=unused, bit0=strobe; strobe is externally inverted)<br>(autolf is wired to GND, all other control/status signals are not connected)
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|F8E3h || F8F3h (later redefined to F8E7h) || Schneiderware Centronics 8255 PPI Control
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|F8E8h || F8F0h,F8F8h || Schneiderware Uni-PIO 8255 PPI #1 Port A ('''without''' pull-ups, with red LEDs)