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15:19, 10 May 2010 The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY of the four upper addresses decoded from the 3 Address pins at the input.