A project to upgrade a CPC6128 to 512K RAM (total), done by replacing the CPC6128's RAM chips, and its PAL banking chip, the project was released 1987 in german magazine ''c't Magazin''.
== Technical ==
The memory is accessed via Port 7Fxxh, as on [[Standard Memory Expansions]]. Since the internal RAM is removed, its total capacity is only 512K (unlike standard 512K expansions which provide 64K internal plus 512K external memory, ie. 576K total). Altogether, the c't expansion works like a 448K dk'tronics expansion (leaving the banks selected via OUT [7Fxxh],FCh..FFh unused).
One half (256K) of the total (512K) expansion memory can be accessed as Video RAM (with normal expansions, only 64 KB are accessible as VRAM). This is making the expansion slightly incompatible with the dk'tronics standard. However, usually expansion memory is mapped to 4000h-7FFFh, whilst VRAM is usually mapped to C000h-FFFFh. So, most existing software may work with it, without accidently displaying garbage on the screen.
== The Circuit ==
* RAMDIS is not supported, not a problem in most cases, but won't work with some special types of expansion hardware, like [[Multiface II]].
* The bank selection for CPU address 4000h..7FFFh does also affect bank bits0-1 for VRAM at 4000h..7FFFh; thus the CRTC may see bank 0-3 in that region (whilst, as far as known, on a normal CPC, it should always see bank 1 in that region).
** '''Notice''' the included sample program '''does''' seem to map VRAM to 4000h, whilst mapping expansion banks to 4000h at the same time. Theoretically, this should result in display glitches - unknown if/how/why the sample works [?]
== Missing Info Memory Configurations ==
* Unknown which banks are usable as VRAM** The first four 16K bank memory is controlled by OUT [7Fxxh],C0h..DFh instructions. Values C0h..C7h are (probably) usuable as VRAM (working same as on all 64K CPC models)** The next four 16K bank are (hopefully) not usuable as VRAM (for CP/M+ compatibility, which uses them as Work normal CPC6128s. Values C8h..DFh do access the additional RAM)** For further banks it's totally unknown if they are used as VRAM or not* Unknown if it's fully dk'tronics compatible, or more like incompletely implemented Inicron (C8h..D3h when using the cut-down 320K upgrade variant* Unknown what happens on accessing the unused region via OUT [7Fxxh],FCh.).FFh == Memory Configurations ==
OUT [7Fxxh],C0h+... 0 1 2 3 4 5 6 7 8..31
== PAL Source Code ==
Below is a typed-up and commented copy of the PALASM source code from the original article.
D7D6 D0 D3 D4 D1 D2 NCAS A15 A14 GND ;pin 1..10
IF (GND) /IOWR=/IOWR ;dummy (do not output anything on this pin)
Some notes on the syntax:
* The first two lines assign the pin-outs. Observe that leading "/" slashes are omitted here. For example, "/CPU" (in schematic) becomes "CPU" (in source code). Accordingly "/CPU" (in source code) would be double-negated "//CPU" aka "CPU" (in schematic).
* The "IF (condition) signal=" part means that "signal" becomes an output when condition is true. In the above source code, condition is always true (VCC), or, for the last 2 lines, always false (GND).
* The "*" and "+" operators are meaning "* = AND", "+ = OR". The idea behind that confusing syntax was to make it "easier" to learn for people who are trained only in basic maths (the formulas do also work when treating *=multiply, and +=plus. For example: 1+0+1+1 = 3 = nonzero = true).
* There must be some priority ordering in the formulas: Either * before +, or operations inside of a line before merging the results of the separate lines (in above examples, both ordering methods do work).
== Newer Info ==