Changes

Aleste 520EX - I/O Ports

156 bytes removed, 06:46, 12 February 2010
/* Gate Array Register 3 - RAM banking (in Aleste's special MAPMOD=1) */
The decoding of the I/O port for the mapper uses bit 15 of the I/O address in the same way as the Aleste "Gate Array".
Address Bit 9,8 define which page.
To avoid writing to the Aleste "Gate-Array" , Data bits 7 and 6 of the data must be 1.
The remaining bits define the RAM block/configuration to use.
 
In CPC mode, writing to the mapper changes the RAM configuration for all pages, with the memory configuration being the same as a DK'Tronics compatible RAM.
In Aleste mapper mode, writing to the mapper changes the RAM for one page.
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