Inputs:
A0..A8 9bit scanline counter (clocked by 3CY aka 1M div sth, reset by HY aka VSYNC) A9 clocked by HSYNC period (duration counted as 1M div sth8 or so)
A10 not used (wired to GND)
Outputs:
0200..03FF: Same as 0000h..01FFh, but with D0 inverted
(ie. "A A F B B B A A 8 8 8 8 8 8 8 8" etc.)
(that is, SYNC is inverted during HSYNC period)
* Note: The "." entries contain a value of 9. (The "." is just used instead of "9" to make the other entries more visible)