Changes

/CHIP SELECT (Input): pin 24 (AY-3-8913 only)

This input signal goes low to enable the PSG to read data on the data bus or write data from the data bus to one of the internal registers. For these above operations to occur, this signal must be true in addition to the current bus address being a valid PSG address. This signal must be valid for all read and write operations. This pin has an internal pull down to Vss.

== ARCHITECTURE ==

All functions of the PSG are controlled through the 16 registers which once programmed, generate and sustain the sounds, thus freeing the system processor for other tasks.

== REGISTER ARRAY ==

Conditioning of the Register Address Latch/Decoder and the Bidirectional Buffers to recognise the bus function required (inactive, latch address, write data, or read data) is accomplished by the Bus Control Decode block.

== SOUND GENERATING BLOCKS ==

Envelope Generator produces an evelope pattern which can be used to amplitude modulate the output of each Mixer.

D/A Converters the three D/A Converters each produce up to a 16 level output signal as determined by the Amplitude Control.

== I/O PORTS ==

Two additional blocks are shown in the PSG Block Diagram which have nothing directly to do with the production of sound -- these are the two I/O ports (A and B). Since virtually all uses of microprocessor-based sound would require interfacing between the outside world and the processor, this facility has been included in the PSG. Data to/from the CPU bus may be read/written to either of two 8-bit I/O Ports without affecting any other function of the PSG. The I/O Ports are TTL-compatible and are provided with internal pull-ups on each pin. Both Ports are available on the AY-3-8910; only I/O Port A is available on the AY-3-8912; no ports are available on the AY-3-8913.

Since all functions of the PSG are controlled by the processor via a series of register loads, a detailed description of the PSG operation can best be acomplished by relating each PSG function to the control of its corresponding register. The function of creating or programming a specific sound or sound effect logically follows the control sequence listed:

Envelope Generator Control R13--R15 Program envelope period and select envelope pattern.

The frequency of each square wave generated by the three Tone Generators (one each for Channels A,B and C) is obtained in the PSG by first counting down the input clock by 16, then by furthur counting down the result by the programmed 12-bit Tone Period value. Each 12-bit value is obtained in the PSG by combining the contents of the relative Course and Fine Tune registers, as illustrated in the following:

R3 B R2

R5 C R4

Course Tone Register Fine Tune Register

12-bit Tone Period (TP) to Tone Generator

Noise Generator Control (Register R6)

Noise Period Register R6 B7 B6 B5 B4 B3 B2 B1 B0

NOT USED 5-bit Noise Period (NP) to Noise Generator

Mixer Control Enable (Register R7)

B A C B A C B A

The amplitudes of the signals generated by each of the three D/A Converters (one each for Channels A,B and C) is determined by the contents of the lower 5-bits (B4--B0) of registers R10,R11 and R12 as illustrated in the following:

The frequency of the envelope is obtained in the PSG by first counting down the input clock by 256, then by furthur counting down the result of the programmed 16-bit Envelope Period value. This 16-bit value is obtained in the PSG by combining the contents of the Envelope Coarse and Fine Tune registers, as illustrated in the following:

16-bit Envelope Period (EP) to Envelope Generator

The Envelope Generator furthur counts down the envelope frequency by 16, producing a 16-state per cycle envelope pattern as defined by its 4-bit counter output, E3 E2 E1 E0. The particular shape and cycle pattern of any desired envelope is accomplished by controlling the count pattern (count up/count down) of the 4-bit counter and by defining a single cycle or repeat-cycle pattern.

B7 B6 B5 B4 B3 B2 B1 B0

NOT USED Hold Alternate Attack Continue