The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).
Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms).
*Playing with the "floating" bus. Using Z80 read I/O commands to write to chip registers. Accessing shadow registers. Using undocumented I/O ports. Writing to multiple chips simultaneously. Changing PPI and PSG ports direction.
*Focusing on the minute details in [[Z80]], [[CRTC]], [[8255|PPI]] and [[PAL16L8|PAL]] chips. They are most often wrong in emulators.
*Examining the [[FDC]] chip. It is only replicated more or less superficially in all emulators because the internals of the chip are still unknown. Many emulators don't even support the FDC SCAN or FORMAT TRACK commands.