== Pipelining ==
The 6502 CPU uses a primitive some sort of pipelining. If an instruction does not store data in memory on its last cycle, the processor can fetch the opcode of the next instruction while executing the last cycle. This is very primitive as the 6502 does not have an instruction cache nor even a prefetch queue. It relies on RAM to hold all program information.
For As an example, the instruction EOR #$FF truly takes 3 cycles:
* On the first cycle, the opcode $49 will be fetched
* During the second cycle the processor decodes the opcode and fetches the parameter #$FF