* On NMOS, when adding a carry to the MSB of an address, a fetch occurs at a garbage address. On CMOS, the last byte of the instruction is refetched.
* On NMOS, when doing a fetch-modify-store instruction (INC, DEC, ASL, LSR, ROL, ROR), garbage is stored into the location during the "modify" cycle... followed by the "real" store cycle which stores the correct data. On CMOS, a second fetch is performed instead of a garbage store.
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== Pipelining ==
The 6502 CPU uses a primitive sort of pipelining. If an instruction does not store data in memory on its last cycle, the processor can fetch the opcode of the next instruction while executing the last cycle.
For example, the instruction EOR #$FF truly takes 3 cycles:
* On the first cycle, the opcode $49 will be fetched
* During the second cycle the processor decodes the opcode and fetches the parameter #$FF
* On the third cycle, the processor will perform the operation and store the result in register A, but simultaneously it fetches the opcode for the next instruction
This is why the EOR instruction effectively takes only 2 cycles.
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