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ASIC
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31 July
/* Vectored interrupt */
|A7..A3||ASIC||IVR register bits7..3
|-
|A2..A1||ASIC||00 = DMA
chan 2,
chan2 ;
01 = DMA
chan 1,
chan1 ;
10 = DMA
chan 0,
chan0 ;
11 = Raster
|-
|A0||ASIC||Always 0
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Phi2x
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