There are two differences between the ASIC implementation of the 8255 PPI and the 8255 PPI inside the CPC:
* When the PPI Control register is re-programmed the output latches are not cleared. In the 8255 PPI used by the CPC and KC Compact the port output *is* cleared. Some games use this fact in the keyboard scanning algorithm, and as a result they will not work on the CPC+.* Port B is always defined as input and Port C is always defined as output.
The PPI in the ASIC is a cut-down version of the 8255PPI. It has all the operations used by the CPC including the bit set/reset feature. It may not have the functions to set the port operation (mode 0, 1 or 2) as these features are not used on the CPC (to my knowledge).
=== Notes ===
* Since the 8255 emulation in the ASIC lacks many features in a real 8255, it is doubtful if the mode operations will work. From the above, it appears that the input/output status of Port B or Port C cannot be controlled.The only port that the input/output status appears to make a difference is with port A.* The ASIC chip is designed to be used in the CPC+ only, and since port B is always used as input and port C is always used as output, it makes sense that the designers did not waste space on the chip to recreate the features of the original chip that were not used.
== CRTC ==