| 0 || x
|}
<br>
{| class="wikitable"
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit 1'' || ''!Bit 0'' || ''!Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
== Video memory structure ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|!rowspan=2|'''Graphics Mode'''||!colspan=8 style="text-align: center;"|'''VRAM byte'''||!colspan=8 style="text-align: center;"|'''Displayed Pixels'''||!rowspan=2|'''Definition'''
|-
|'''!7'''|'''!6'''|'''!5'''|'''!4'''|'''!3'''|'''!2'''|'''!1'''|'''!0'''|'''!1'''|'''!2'''|'''!3'''|'''!4'''|'''!5'''|'''!6'''|'''!7'''|'''!8'''
|-
|0