== Vectored Interrupt ==
In this mode, interrupts are prioritized in a fixed sequence. The raster ASIC provides an interrupt has the highest priority, followed by DMA channels 2 down to 0 respectivelyvector on interrupt request.
The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the interrupt vector provided by the ASIC to the CPU are as follows: 00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA raster.
Bit0 of the IVR controls whether DMA channel interrupts are automatically cleared.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
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