Changes

Default I/O Port Summary

13 bytes removed, 5 July
/* Memory Mapped I/O Ports */
== I/O Ports ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|'''!I/O'''||'''!Decoded as'''||'''!Port'''||'''!Read'''||'''!Write'''
|-
|#7FXX||%01xxxxxx xxxxxxxx||[[Gate Array]]||-||Write
== Memory Mapped I/O Ports ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|'''!Mem'''||'''!Decoded as'''||'''!Port'''||'''!Read'''||'''!Write'''
|-
|#4000-7FFF||%01xxxxxx xxxxxxxx||ASIC - CPC+/GX4000 registers|| Read || Write
The [[ASIC]] I/O page is defined as follows:
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"! ADDR !! SIZE !! POR !! TYPE !! MNEM !! USE
|-
| 4000h || 100h || N || R/W || || Sprite 0 image data
| 4F00h || 100h || N || R/W || || Sprite 15 image data
|-
| style="background:#efefef;" colspan="6"|''Block unused''
|-
| 6000h || 2 || N || R/W || X0 || Sprite 0 X position
| 607Dh || 3 || || || || (unused)
|-
| style="background:#efefef;" colspan="6"|''Block unused''
|-
| 6400h || 2 || N || R/W || || Colour palette, pen 0
| 643Eh || 2 || N || R/W || || Colour palette, sprite colour 15
|-
| style="background:#efefef;" colspan="6"|''Block unused''
|-
| 6800h || 1 || Y || W || PRI || Programmable raster interrupt scan line
| 680Fh || 1 || || R || ADC7 || Analogue input channel 7
|-
| style="background:#efefef;" colspan="6"|''Block unused''
|-
| 6C00h || 2 || N || W || SAR0 || "DMA" channel 0 address pointer
| 6C0Fh || 1 || Y || R/W || DCSR || "DMA" control/status register
|-
| style="background:#efefef;" colspan="6"|''Block unused''
|}
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