'''Notes'''
* On types CRTCs 0 and /1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.
* CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split-screen and 8-bit printer port functionalities specific to the ASIC.
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=== Horizontal and Vertical Sync (R3) Reading from CRTC registers on ASIC/Pre-ASIC ===
Type 0:*Bits 7..On CRTCs 3/4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits , only the 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.least significant bits of the selected register number are considered to read a register according to the following table:
Type 1{|{{Prettytable|width:700px; font-size: 2em;}}*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.|'''Nb'''||'''Register'''||'''Definition'''*Bits 3..|-|0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.||R16||Light Pen Address (High)|-|1||R17||Light Pen Address (Low)|-|2||R10||Cursor Start Raster|-|3||R11||Cursor End Raster|-|4||R12||Display Start Address (High)|-|5||R13||Display Start Address (Low)|-|6||R14||Cursor Address (High)|-|7||R15||Cursor Address (Low)|}
Type 2:*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16. Types 3/4:*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16. <br> === Interlace and Skew (R8) === Types 0/3/4:*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 3..2 are ignored.*Bits 1..0 define the interlace mode (00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video). Types 1/2:*Bits 7..2 are ignored.*Bits 1..0 define the interlace mode. 2 interlace modes are available:* In interlace sync modeTherefore, the same information is painted in both fields to enhance readability. In this mode, reprogramming the CRTC is not necessary* In interlace sync and video mode, alternating lines are displayed in the even and odd field to double the resolution. In this mode, it is necessary to reprogram the CRTC as if we were building a frame of 624 lines. The 625th line is managed automatically by the CRTC[[File:CRTC Interlace modes.png]] <br> === Vertical Displayed (R6) === On CRTCs 0/1/2an example, the condition VCC=R6 is considered immediately to activate the VBORDER. The only exception is for CRTC 1 with a value of 0, which triggers an immediate BORDER without the condition VCC=R6 being required. On CRTCs 3/reading register 4, will give the condition VCC=R6 is tested only at new character line start. The update of R6 during the character line is therefore not considered. <br> === R31 on Type 1 === R31 is described in the UM6845R documentation same result as "Dummy Register". Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register. In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff. R31 doesn't exist on CRTCs 0/2/3/4. <br> === Status reading register on Type 1 === The UM6845R has a status register that can be read using port &BExx. Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 12 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read. Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6. It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.This bit will be 0 when pixels are being displayed. All the other bits read as 0 and don't have any function20.
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=== Reading from CRTC registers on ASIC/Pre-ASIC Horizontal and Vertical Sync (R3) ===
On CRTCs 3/Type 0:*Bits 7..4, only the define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3 least significant bits of the selected register number are considered to read a register according to the following table:..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
{|{{Prettytable|widthType 1: 700px; font-size: 2em;}}|'''Nb'''||'''Register'''||'''Definition'''*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.|-|*Bits 3..0||R16||Light Pen Address (High)|-|1||R17||Light Pen Address (Low)|-|2||R10||Cursor Start Raster|-|3||R11||Cursor End Raster|-|4||R12||Display Start Address (High)|-|5||R13||Display Start Address (Low)|-|6||R14||Cursor Address (High)|-|7||R15||Cursor Address (Low)|}define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
ThereforeType 2:*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16. Types 3/4:*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16. <br> === Interlace and Skew (R8) === Types 0/3/4:*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 3..2 are ignored.*Bits 1..0 define the interlace mode (00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video). Types 1/2:*Bits 7..2 are ignored.*Bits 1..0 define the interlace mode. 2 interlace modes are available:* In interlace sync mode, the same information is painted in both fields to enhance readability. In this mode, reprogramming the CRTC is not necessary* In interlace sync and video mode, alternating lines are displayed in the even and odd field to double the resolution. In this mode, it is necessary to reprogram the CRTC as an exampleif we were building a frame of 624 lines. The 625th line is managed automatically by the CRTC[[File:CRTC Interlace modes.png]] <br> === Vertical Displayed (R6) === On CRTCs 0/1/2, reading register the condition VCC=R6 is considered immediately to activate the VBORDER. The only exception is for CRTC 1 with a value of 0, which triggers an immediate BORDER without the condition VCC=R6 being required. On CRTCs 3/4 will give , the same result condition VCC=R6 is tested only at new character line start. The update of R6 during the character line is therefore not considered. <br> === R31 on Type 1 === R31 is described in the UM6845R documentation as reading "Dummy Register". Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register. In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff. R31 doesn't exist on CRTCs 0/2/3/4. <br> === Status register 12 on Type 1 === The UM6845R has a status register that can be read using port &BExx. Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or 20R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read. Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6. It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.This bit will be 0 when pixels are being displayed. All the other bits read as 0 and don't have any function.
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=== Vertical Adjustment mode ===
On CRTCs 03/4, this mode does not increment VCC, so VCC remains equal to R4. On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once. On CRTCs 1/2, this mode increments VCC and so VCC goes beyond , causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.
Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, this mode does not increment VCC and so VCC stays equal during Vertical Adjustment, C9 has to R4fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.
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