CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.
== CUDISP (aka CURSOR) ==
CUDISP (Cursor Display) signal defines the hardware cursor.
CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.
However, this signal is provided to the expansion port. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
== DISPTMG (aka Display Enable) ==
DISPTMG (Display Timing) signal defines the border. When DISPTMG is "10" the border colour is output by the Gate-Array to the display.
The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
The DISPTMG can be forced to 0 by using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.
== HSYNC and VSYNC ==
On CPC, HSYNC and VSYNC from the CRTC are passed into to the [[Gate-Array]] for further modification. See its wiki page.
When The HSYNC width value is active Gate-Array outputs the palette colour blackinterpreted differently between CRTCs. If the On CRTCs 0/1, if 0 is programmed no HSYNC is set to 14 characters then black will be output for 14usgenerated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.
The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51. On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array. The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width. CRTCs 1 and /2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 on CRTCs 0, /3 and /4. If 0 is programmed this gives 16 lines of VSYNC.
The bit 0 of port B of the PPI changes to 1 as soon as the VSYNC signal is produced by the CRTC.
|2||Horizontal Sync Position ||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 only on some CRTCs. Needs to be at least 2 for Gate Array to change the video mode); VSync width in scan-lines (0 always means 16. Not present on all CRTCs, fixed to 16 lines on these).
|-
|4||Vertical Total (-1)||x0000000||38||Height of the screen, in characters.
! Abbr
! Alternate name
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|
|-
|Horizontal Sync Counter
|HSC
|C3l
|
|-
|Vertical Character Counter
|VCC
|C4
|
|-
|Vertical Sync Counter
|VLC
|C9
|If non-interlace, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5 (or C9 |This counter does not exist on CRTCs 0/3/4). C9 is reused instead
|-
|Frame Counter
|FC
|''|Used for to alternate frames in interlace and for CRTC cursor blinking''|-|Memory Address|MA||This counter is exposed on CRTC pins MA0..MA13
|}
No matter its type, the CRTC never buffers its counters.
The only value that is saved in a buffer in the CRTC is the video pointer MA because it is reloaded at each line start.
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