UM6845:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
UM6845R:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
MC6845:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
Pre-ASIC/ASIC:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===