All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.
<br>
== The 8255 in the CPC ==
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Group Mode 1 (Strobed Input/Output) and Group Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program. Group Mode 0 (Basic Input/Output) is always used.
In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the [https://cpctech.cpcwiki.de/docs/cpcplus.html Extra CPC+ documentation] for more information.
* Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program, Mode 0 (Basic Input/Output) is always used.<br>
== Port Usage ==
* NOTE - If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.
<br>
== PPI Port A ==
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<br>
== PPI Port B ==
* If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.
* For more info on LK1-LK4 (and further LKs) see [[LK Links]]
<br>
== PPI Port C ==
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<br>
== PPI Control ==
This register has two different functions depending on bit7 of the data written to this register.
<br>
=== PPI Control with Bit7=0 ===
Bit 7 SF Must be "0" in this case
[[File:Intel 8255A - BSR control word format8255 Control0.jpgpng]] <br>
=== PPI Control with Bit7=1 ===
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.
[[File:Intel 8255A - IO modes control word format8255 Control1.jpgpng]] <br>
== Group Modes ==
In some of these modes , port C is used as a control/status port for port A or B. It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the user to set or reset any individual bits in port C. <br>
=== Mode 0 – Simple Input/output mode ===
In this mode , the 8 bit port A (PA0-PA7) of 8255 IC ports can be configured as input or output portused for simple I/O operations without handshaking signals. In the similar fashion Port A, port B (PB0-PB7) can also configured as input or output provide simple I/O operation. However there is flexibility for the The two halves of port C. It can be divided into two either used together as an additional 8-bit port, or they can be used as individual 4 -bit ports, . Since the two halves of port CLower (PC0-PC3) and port CUpper (PC4-PC7). Each of them can set independently for input or output operation. In this way we can say there C are four ports (port-Aindependent, portthey may be used such that one-B, port CLower and port CUpper) and each of them can set either half is initialized as an input port or while the other half is initialized as an output port. Here these ports are simple input or output ports. That means these ports can work without handshaking. In this mode the outputs are latched whereas the inputs are not latched.
[[File:8255 - mode-0.png]]
<br>
=== Mode 1 – Strobed Input/output or Handshake mode ===
Mode 1 is a second mode of 8255 I/O mode. In this mode of operation handshaking can used When we wish to use port A or port B for the handshake (strobed) input or output data transfer. Another important think operation, we have to remember initialise that there are two groups port in 8255 PPI, Group mode 1 (port A and Group port Bcan be initialised to operate in different modes, i. Both these groups have one 8-bit port and one 4-bit porte.Group A consist Port-, for e.g., port A can operate in mode 0 and Port CUpper. And group port B consist Port-B and Port CLowerin mode 1). The 8-bit Some of the pins of port C function as handshake lines. For port B in this mode (irrespective of each group can be programmed for whether is acting as an input port or output operation with latched port), PC0, PC1 and PC2 pins function as handshake lines. If port A is initialised as mode 1 input port, then, PC3, PC4 and latched output facilitiesPC5 function as handshake signals. The bits of Port C used Pins PC6 and PC7 are available for handshakinguse as input/output lines.
[[File:8255 - mode-1.png]]
<br>
=== Mode 2 – Bidirectional Mode ===
So the final mode of 8255 is Mode 2. In Only port A can be initialized in this mode . Port A can be programmed to operate as a used for bidirectional porthandshake data transfer. When Port This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A programmed in this mode . The remaining pins of operation, Port B port C (PC0 - PC2) can be used either as input/output lines if group B is initialized in Mode mode 0 or Mode as handshaking for port B if group B is initialized in mode 1. For mode 2 operation PC3 to PC7 bits used for handshaking. In this mode too both inputs , the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes to and outputs from a floppy disk controller. Acknowledgement and handshaking signals are latchedprovided to maintain proper data flow and synchronisation between the data transmitter and receiver.
[[File:8255 - mode-2.png]]
<br>
=== Port pins summary ===
[[File:8255 - Port pins.gif]]
<br>
== Programming Examples ==
</pre>
= Diagram =<br>
[[File:== Block-diagram-of-8255-l.jpg]]Diagram ==
= Resources =[[File:8255 Block Diagram.png]]
<br> == Amstrad ASIC PPI == *The 8255 PPI is not emulated by the Pre-ASIC. These CPCs have a real PPI chip and therefore behave like the first generation of CPCs.*The ASIC PPI does not support Group Modes other than Groupe Mode 0.*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports. <br> == Resources == * [[Media:Intel_8255A_DatasheetIntel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PIO]]PPI
<br> == Links ==
*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]
*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)]
[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]