The available commands are :
*0RDDh LOAD R,D Load 8 bit data D to PSG register R (0R015)*1NNNh PAUSE N Pause for N prescaled ticks (0<No4095)*2NNNh REPEAT N Set loop counter to N for this stream (0<No4095)and mark next instruction as loop start.*3xxxh (reserved) Do not use*4000h NOP No operation (64us idle)*4001h LOOP If loop counter non zero, loop back to the first instruction after REPEAT instruction and decrement loop counter.*4010h INT Interrupt the CPU (see section 2.7 below)*4020h STOP Stop processing the sound list.
Note that :
The exact timing is based on 1us cycles as follows. After the leading edge from HSYN from the 6845 there is one dead cycle followed by an instruction fetch cycle for each channel which is active (i.e. enabled and not paused). The execute cycles then follow for each active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register write.
===Interrupt service===