== Last news about this project ==
In MaY 2019, I add cassette feature.
In August 2018, totally desperated -around time and level of efforts- about reaching next step focus around Z80 range, here came Sorgelig, he is working around port of FPGAmstrad into the MiSTer FPGA platform, and make during his step an intermediate jump step on MiST-board called "Amstrad_MiST" full of verilog as he seems to love. And, as a specialist of Z80 core, I just send him Z80 testbenches I collected since, he then corrected the Z80 fully this way, I merged, resulting this next current checkpoint.