HALT is the only one instruction that will be always OK on plustest.dsk instruction timing testbench. As this instruction cannot be timed.
plustest.dsk testbench 5 does pass, except for two not implemented instruction : CPIR and CPDR (that does currently the same as CPI and CPD) - btw its instruction instructions are using then same slower than CPI/CPD : none.(no WAIT_n added for theses instructions)
==== GA: WAIT_n generator - plustest.asm ====