Changes

The exact timing is based on 1us cycles as follows. After the leading edge from HSYN HSYNC from the 6845 there is one dead cycle followed by an instruction fetch cycle for each channel which is active (i.e. enabled and not paused). The execute cycles then follow for each active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register write. Example 1: If DMA channel 0 and 2 are active: <dead cycle>, <instruction fetch dma channel 0>, <instruction fetch dma channel 2>, <instruction execute dma channel 0>,<instruction execute dma channel 2> Example 2: If DMA channel 2 is only active: <dead cycle>,<instruction fetch dma channel 2>,<instruction execute dma channel 2>