It is confirmed that the ASIC restores:
* 8255 (within ASIC) Port A direction. A test used the DMA to write to * AY selected register 7 of the * AY. While this was happening the data was read from register 7 and sent /write operation AY "inactive" state appears to the border. The border did change colourbe needed for register selection only. If the direction had not been restored the border would have remained a single colourIt doesn't appear to be needed for each AY register read/write operation.
The exact timing is based on 1us cycles as follows. After the leading edge from HSYN from the 6845 there is one dead cycle followed by an instruction fetch cycle for each channel which is active (i.e. enabled and not paused). The execute cycles then follow for each active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register write.