== Technical ==
Connects between Z80 CPU and mainboard. Uses a 1.8432MHz oscillatorI/O Ports for AMSSIO v1, MC14411P bit rate generatorv2, a 6850 ACIA, a MAX232 voltage converter, and 74LS04 and 74LS08 logic chips.v3 are:
Port addresses, schematics, and differences between versions I-III are unknown FBF0h AMSSIO Serial Interface [[MC6850|6850 ACIA chip]] Control/Status Register (the R/W) FBF1h AMSSIO webpage doesn't exist anymoreSerial Interface [[MC6850|6850 ACIA chip]] Data Register (R/W).
* For details on the MC6850 chip, see [[6850 ACIA chip]]. Observe that the baudrate CLK sources differ for v1,v2,v3. In v3 the CLK is fixed, v1/v2 have different jumper-selectable CLKs. And, the photo shows a different CLK crystal than the schematic. So, don't expect different AMSSIOs to be compatible with each other. ---- '''AMSSIO-II (v4)'''
== Software ==