3,255 bytes added,
11:24, 23 February 2010 The Intel 8237 is a four channel DMA controller (also used in IBM PCs).
== Usage in CPC ==
Used by [[Magic Sound Board]] for [[Aleste 520EX]]:
Port F8D0h..F8DFh - DMA Controller
Clock source comes from two 8254 chips.
TC triggers NMI.
The 64K address space is broken to four virtual 16K banks, allowing to
access up to 48K without alignment restrictions, or 64K with 16K alignment.
No restriction on crossing 64K boundaries. The whole 512K are address-able.
== Registers ==
=== Port 00h..07h - Channel 0..3 Address/Length (R/W) ===
* Port 00h - Channel 0 Address (LSB,MSB) (R/W)
* Port 01h - Channel 0 Length (LSB,MSB) (R/W)
* Port 02h - Channel 1 Address (LSB,MSB) (R/W)
* Port 03h - Channel 1 Length (LSB,MSB) (R/W)
* Port 04h - Channel 2 Address (LSB,MSB) (R/W)
* Port 05h - Channel 2 Length (LSB,MSB) (R/W)
* Port 06h - Channel 3 Address (LSB,MSB) (R/W)
* Port 07h - Channel 3 Length (LSB,MSB) (R/W)
Writing sets the initial (reload) and current (remaining) value; both to the
same value. Reading returns only the current (remaining) value. Address and
Length are 16bit each, split into two accesses:
1st access - LSB
2nt access - MSB
The 1st/2nd access flipflop can be reset via writing to Port 0Ch (or 0Dh).
=== Port 08h - Status Register (R) ===
0-3 Channel 0..3 Reached TC (0=No, 1=Yes)
4-7 Channel 0..3 Request (0=No, 1=Yes)
=== Port 08h - Command Register (W) ===
0 Memory-to-memory (0=Disable, 1=Enable)
1 Channel 0 Address Hold (0=Disable, 1=Enable) ;ignored if bit0=0
2 Controller Disable (0=Enable, 1=Disable)
3 Timing (0=Normal, Compressed) ;ignored if bit0=1
4 Polarity (0=Fixed, 1=Rotating)
5 Write Selection (0=Late, 1=Extended) ;ignored if bit3=1
6 DREQ Sense Active (0=High, 1=Low)
7 DACK Sense Active (0=Low, 1=High)
=== Port 09h - Request Register (W) ===
0-1 Channel Number (0..3=Channel 0..3)
2 Request Bit for that channel (0=Cleared, 1=Set)
4-7 Not used
=== Port 0Ah - Single Bit - Mask Register (W) ===
0-1 Channel Number (0..3=Channel 0..3)
2 Mask Bit for that channel (0=Cleared/Enable DREQ, 1=Set/Disable DREQ)
4-7 Not used
Changes a single mask bit (one can also change ALL bits via Port 0Fh).
=== Port 0Bh - Mode Register (W) ===
0-1 Channel Number (0..3=Channel 0..3)
2-3 Transfer Mode (0=Verify, 1=Write, 2=Read, 3=Illegal) ;ignored if Cascade
4 Autoinitialize (0=Disable, 1=Enable)
5 Address Step (0=Increment, 1=Decrement)
6-7 Mode Select (0=Demand, 1=Single, 2=Block, 3=Cascade)
=== Port 0Ch - Clear Byte Pointer Flipflop Command (W) ===
Writing any value sets the flipflop (for Port 0..7) to first access state.
=== Port 0Dh - Temporary Register (R) ===
Contains the most recently transferred byte.
=== Port 0Dh - Master Clear Command (W) ===
Writing any value resets the chip (same as hardware reset). Sets the Mask
bits, and clears most other registers.
=== Port 0Eh - Reserved (8237), or Clear Mask Register (8237A) (W) ===
Reserved (on 8237, at least).
=== Port 0Fh - All Bit - Mask Register (W) ===
0-3 Channel 0..3 Mask Bits (0=Cleared/Enable DREQ, 1=Set/Disable DREQ)
4-7 Not used