Most CPC interfaces should contain the DART chips. Eventually some might use the SIO chips (which are including some additional features).
* Zilog Z8470 - Z80 DART (Dual-channel Asynchronous Receiver Transmitter) * Zilog Z8440 - Z80 SIO (Dual-channel Serial Input/Output Controller)
Note: Five different variants of the SIO chips exist: types 0/1/2 are 40pin DIP chips with slightly different features/pinouts, types 3 (QFP package) and 4 (PLCC package) are 44pin chips, both combining all features of the three 40pin chips.
== Control/Status Registers==
In the default state, reads/writes on the Control/Status port are accessing the RR0/WR0 registers. After writing a non-zero index value "n" to Bit0-2 of WR0, the next read/write operation on the Control/Status port will access the corresponding RRn/WRn register.