Changes

= Snapshot (.SNA) file format =

The format was first defined for the [[CPCEMU|CPCEMU]] emulator but is now widely supported. The format was originally defined by [[Marco Vieth|Marco Vieth]]. Version 3 was defined by [[Ulrich Doewich|Ulrich Doewich]], [[Martin Korth|Martin Korth]], [[Richard Wilson|Richard Wilson]] and [[Kevin Thacker|Kevin Thacker]].

There are 3 versions defined in this document. Version 3 is the most recent and is currently supported by a few of the most recent emulators.

*[[Gate Array|GA = Version 1 "Gate Array"]] *[[CRTC|CRTC ="6845 Cathode Ray Tube Controller"]] *[[8255|PPI = "Intel 8255 Programmable Peripheral Interface"]] *[[PSG|PSG = "AY-3-8912 Programmable Sound Generator"]]

= Version 1 = {|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Count''||''Description''

|00-07''Offset (Hex)''|''Count''|8||The identification string "MV - SNA". This must exist for the snapshot to be valid.''Description''

|0800-0f|07|8||(not used; set The identification string "MV - SNA". This must exist for the snapshot to 0)be valid.

|1008-0f|8|1||snapshot version (1not used; set to 0)

|1110|1|snapshot version (1||Z80 register F)

|12|11|1||Z80 register AF

|13|12|1||Z80 register CA

|14|13|1||Z80 register BC

|15|14|1||Z80 register EB

|16|15|1||Z80 register DE

|17|16|1||Z80 register LD

|18|17|1||Z80 register HL

|19|18|1||Z80 register RH

|1a|19|1||Z80 register IR

|1b|1a|1||Z80 interrupt flip-flop IFF0 (note 2)register I

|1c|1b|1||Z80 interrupt flip-flop IFF1 IFF0 (note 2)

|1d|1c|1||Z80 register IX (low) interrupt flip-flop IFF1 (note 52)

|1e|1d|1||Z80 register IX (highlow) (note 5)

|1f|1e|1||Z80 register IY IX (lowhigh) (note 5)

|20|1f|1||Z80 register IY (highlow) (note 5)

|21|20|1||Z80 register SP IY (lowhigh) (note 5)

|22|21|1||Z80 register SP (highlow) (note 5)

|23|22|1||Z80 register PC SP (lowhigh) (note 5)

|24|23|1||Z80 register PC (highlow) (note 5)

|25|24|1||Z80 interrupt mode register PC (0,1,2high) (note 35)

|26|25|1||Z80 register F' interrupt mode (0,1,2) (note 43)

|27|26|1||Z80 register AF' (note 4)

|28|27|1||Z80 register CA' (note 4)

|29|28|1||Z80 register BC' (note 4)

|2a|29|1||Z80 register EB' (note 4)

|2b|2a|1||Z80 register DE' (note 4)

|2c|2b|1||Z80 register LD' (note 4)

|2d|2c|1||Z80 register HL' (note 4)

|2e|2d|1||GA: index of selected pen Z80 register H' (note 104)

|2f-3f|2e|1||GA: current palette index of selected pen (note 1110)

|40|2f-3f|1||GA: multi configuration current palette (note 1211)

|41|40|1||current RAM GA: multi configuration (note 1312)

|42|41|1||CRTC: index of selected register current RAM configuration (note 1413)

|43-54|42|1||CRTC: index of selected register data (0..17) (note 1514)

|55|43-54|1||current ROM selection CRTC: register data (0..17) (note 1615)

|56|55|1||PPI: port A current ROM selection (note 616)

|57|56|1||PPI: port B A (note 76)

|58|57|1||PPI: port C B (note 87)

|59|58|1||PPI: control port C (note 98)

|5a|59|1||PSGPPI: index of selected register control port (note 179)

|5b-6a|5a|1||PSG: index of selected register data (0,1,....15note 17)

|6b5b-6a|1|6c||memory dump size in Kilobytes PSG: register data (e0,1,.g. 64 for 64K, 128 for 128k) (note 18..15)

|6d-ff6b|6c|1||not used set to 0memory dump size in Kilobytes (e.g. 64 for 64K, 128 for 128k) (note 18)

|1006d-...|ff|1||memory dumpnot used set to 0

== Notes ==

1. All multi-byte values are stored in little-endian format (low byte followed by higher bytes).

2. "IFF0" reflects the state of the maskable interrupt (INT). "IFF1" is used to store the state of IFF0 when a non-maskable interrupt (NMI) is executed. Bit 0 of these bytes is significant. For CPCEMU compatibility, these bytes should be set to "1" when the IFF flip-flop is "1" and "0" when the flip-flop is "0". For compatibility with other emulators, bits 7-1 should be set to "0". When bit 0 of "IFF0" is "0" maskable interrupts will be ignored. When bit 0 of "IFF1" is "1" maskable interrupts will be acknowledged and executed. See the document about the Z80 for more information.

3. This byte will be 0, 1 or 2 for the interrupt modes 0, 1 or 2. The interrupt mode is set using the "IM x" instructions. See the document about the Z80 for more information.

4. These registers are from the alternate register set of the Z80.

5. These registers are 16-bit. "low" indicates bits 7..0, "high"indicates bits 15..8.

6. This byte represents the inputs to PPI port A regardless of the input/output setting of this port.

7. This byte represents the inputs to PPI port B regardless of the input/output setting of this port.

8. This byte represents the outputs from port C regardless of the input/output setting of this port.

9. This byte represents the PPI control byte which defines the input/output and mode of each port and not the last value written to this port. For CPCEMU compatibility bit 7 of this byte must be set to "1".

10. This byte in the snapshot represents the selected pen register of the Gate-Array. This byte is the last value written to this port. Bit 7,6,5 should be set to "0".

11. This byte in the snapshot represents the multi-configuration register of the Gate-Array. This byte is the last byte written to this register. For CPCEMU compatibility, bit 7 should be set to "1" and bit 6 and bit 5 set to "0".

12. These bytes are the current palette. For CPCEMU compatibility, these bytes should have bit 7=bit 6=bit 5="0". Bits 4..0 define the colour using the hardware colour code. The colours are stored in the order pen 0, pen1, pen 2,...,pen 15 followed by border colour.

13. This byte represents a ram configuration for a Dk'Tronics/Dobbertin/Amstrad compatible RAM expansion, or the built in RAM expansion of the CPC6128 and CPC6128+. Bits 5..0 define the ram expansion code. For CPCEMU compatibility, bit 7 and bit 6 of this byte should be set to "0".

14. This byte in the snapshot represents the index of the currently selected CRTC register. For compatibility with CPCEMU this value should be in the range 0-31.

15. These bytes represent the data of the CRTC's registers.

16. This byte in the snapshot represents the last byte written to the "ROM select" I/O port.

17. This byte in the snapshot represents the index of the currently selected PSG register. For CPCEMU compatibility, this byte should be in the range 0-15.

18. the first 64k is always the base 64k of ram. The second 64k (if present) is the additional ram in a Dk'Tronics/Dobbertin/Amstrad compatible RAM expansion or the internal ram of the CPC6128/CPC6128+. The memory dump is not dependant on the current RAM configuration. Note that CPCEMU can only write a 64K or 128K snapshot.

= Changes and additions in Version 2 from Version 1 =

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Count''||''Description''

|10''Offset (Hex)''|''Count''|1||snapshot version (2)''Description''

|6d|10|1||CPC Type:* 0 = CPC464* 1 = CPC664* snapshot version (2 = CPC6128* 3 = unknown )

|6e|6d|1||interrupt number (CPC Type: *0..5) (note 1a)= CPC464 *1 = CPC664 *2 = CPC6128 *3 = unknown 

|6f-746e|1|6||6 multimode bytes interrupt number (0..5) (note 1b1a)

|756f-ff||x74|6|6 multimode bytes (not usednote 1b)

== Notes ==

1. If standard CPC raster interrupts are used, interrupts are acknowledged and "executed" at the time they are requested, then there will be 6 interrupts executed per screen update cycle.

* CPCEMU uses a simple system to emulate the interrupts. It is assumed there are exactly 6 interrupts per screen update cycle (the interrupts are assumed to occur at a frequency of 300Hz). This byte records the interrupt number in the current screen update cycle. More accurate emulators use the correct interrupt generation method and may ignore this byte. For CPCEMU compatibility, these emulators should set this byte to "0".

* CPCEMU uses a simple system to emulate the screen display. It allows the mode to be changed in each of the 6 interrupts that occur during a single 50Hz/60Hz period. These bytes represent the mode in each of these sections, i.e. the screen modes (0,1 or 2) for the interrupts 0..5. More accurate emulators support changing of the screen mode at any point supported by the Amstrad hardware, these emulators should write "0" for all these bytes.

= Changes and additions in Version 3 from Version 2 =

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Count''||''Description''

|10''Offset (Hex)''|''Count''|1||snapshot version (3)''Description''

|6d|10|1||CPC Type:* 0 = CPC464* 1 = CPC664* 2 = CPC6128* snapshot version (3 = unknown * 4 = 6128 Plus* 5 = 464 Plus * 6 = GX4000)

|9c|6d|1||FDD motor drive state (CPC Type: *0=off, CPC464 *1=on)CPC664 *2 = CPC6128 *3 = unknown *4 = 6128 Plus *5 = 464 Plus *6 = GX4000 

|9d-a0|9c|1||FDD current physical track motor drive state (note 150=off, 1=on)

|a1|9d-a0|1||Printer Data/Strobe Register FDD current physical track (note 115)

|a4|a1|1||CRTC type:* 0 = HD6845SPrinter Data/UM6845* Strobe Register (note 1 = UM6845R* 2 = MC6845* 3 = 6845 in CPC+ ASIC* 4 = 6845 in Pre-ASIC )

|a9|a4|1||CRTC horizontal character counter register (note 11)type: *0 = HD6845S/UM6845 *1 = UM6845R *2 = MC6845 *3 = 6845 in CPC+ ASIC *4 = 6845 in Pre-ASIC 

|aa|a9|1||unused CRTC horizontal character counter register (0note 11)

|ab|aa|1||CRTC character-line counter register unused (note 20)

|ac|ab|1||CRTC rastercharacter-line counter register (note 32)

|ad|ac|1||CRTC vertical total adjust raster-line counter register (note 43)

|ae|ad|1||CRTC horizontal sync width vertical total adjust counter register (note 54)

|af|ae|1||CRTC vertical horizontal sync width counter (note 65)

|b0-b1|af|1||{|{{Prettytable|CRTC vertical sync width: 700px; font-size: 2em;}}|''Bit''||''Function'' counter (note 6)

|0b0-b1||if "1" VSYNC is active, if "0" VSYNC is inactive (note 8)| {|

|1''Bit''||if "1" HSYNC is active, if "0" HSYNC is inactive (note 9)''Function''

|2-70||reservedif "1" VSYNC is active, if "0" VSYNC is inactive (note 8)

|7|1|if "1" Vertical Total Adjust HSYNC is active, if "0" Vertical Total Adjust HSYNC is inactive (note 109)

|82-157||Reserved (0)reserved

|}7| if "1" Vertical Total Adjust is active, if "0" Vertical Total Adjust is inactive (note 10)

|b28-15||1||GA vsync delay counter Reserved (note 140)|} 

|b3|b2|1||GA interrupt scanline vsync delay counter (note 1214)

|b4|b3|1||interrupt request flag (0=no interrupt requested, 1=GA interrupt requested) scanline counter (note 1312)

|b5-ffb4|1|75||unused interrupt request flag (0=no interrupt requested, 1=interrupt requested) (note 13)

== Notes ==

Notes:

1. This byte in the snapshot represents the last byte written to the printer I/O port (this byte does not include the automatic inversion of the strobe caused by the Amstrad hardware).

2. This register is internal to the CRTC and counts the number of character-lines. The counter counts up. This value is in the range 0-127. (This counter is compared against CRTC register 4).

3. This register is internal to the CRTC and counts the number of raster-lines. The counter counts up. This value is in the range 0-31. (This counter is compared against CRTC register 9).

4. This register is internal to the CRTC and counts the number of raster-lines during vertical adjust. The counter counts up. This value is in the range 0-31. This should be ignored if the CRTC is not "executing" vertical. adjust.(This counter is compared against CRTC register 5).

5. This register is internal to the CRTC and counts the number of characters during horizontal sync. This counter counts up. This value is in the range 0-16. This should be ignored if the CRTC is not "executing" horizontal sync. (This counter is compared against CRTC register 3).

6. This register is internal to the CRTC and counts the number of scan-lines during vertical sync. This counter counts up. This value is in the range 0-16. This should be ignored if the CRTC is not "executing" vertical sync. (This counter is compared against CRTC register 3).

7. These bytes define the internal state of the CRTC. Each bit in these bytes represents a state.

8. When VSYNC is active, the CRTC is "executing" vertical sync, and the vertical sync width counter in the snapshot is used.

9. When HSYNC is active, the CRTC is "executing" horizontal sync width counter in the snapshot is used.

10. When Vertical total adjust is active, the CRTC is "executing" vertical total adjust and the vertical total adjust counter in the snapshot is used.

11. This register is internal to the CRTC and counts the number of characters. This counter counts up. This value is in the range 0-255. (This counter is compared against CRTC register 0).

12. This counter is internal to the GA and counts the number of HSYNCs. This counter is used to generate CPC raster interrupts. This counter counts up. This value is in the range 0-51.

13. This flag is "1" if a interrupt request has been sent to the Z80 and it has not yet been acknowledged by the Z80. (A interrupt request is sent by the GA for standard CPC raster interrupts or by the ASIC for raster or dma interrupts).

Immediatly following the memory dump there is optional data which is seperated into chunks.

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Count''||''Description''

|0''Offset (Hex)''|''Count''|4||Chunk name (note 1)''Description''

|4|0|4||Chunk data length name (note 21)

Notes:

1. The chunks are defined with 4-byte character codes. (e.g. "CPC+"). In this example, the 4-byte character code would be stored in the file as 'C' then 'P' then 'C' then '+'.

2. The "Chunk data length" defines the length of data following the header and does not include the size of the header. This number is stored in little endian format.

3. If a emulator finds a chunk which it does not support then it should skip the chunk and continue with the next chunk in the file. Therefore an emulator author may add emulator specific chunks to the file and it will not prevent the snapshot from being used with other emulators that do not recognise the added chunks.

=== CPC+ Chunk ===

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Length''||''Addr in ASIC register-ram''||''Description''

|000-7FF''Offset (Hex)''|''Length''|800||4000''Addr in ASIC register-4FFFram''||Sprite Bitmaps (note 1)''Description''

|800000-87F7FF|800|8*16||60004000-607F|4FFF|Sprite Attributes (see below) Bitmaps (note 21)

|880800-8BF87F||328*216||64006000-643F607F||Palettes Sprite Attributes (see below) (note 32)

|8C0880-8BF|32*2|16400-643F||6800||Programmable Raster Interrupt Palettes (note 43)

|8C1|8C0|1|6800|6801||Screen split scan-line Programmable Raster Interrupt (note 4)

|8C28C1|1|2||6802-6803|6801|Screen split secondary screenscan-address line (note 4)

|8C48C2|2|16802-6803||6804||Soft scroll control register Screen split secondary screen-address (note 4)

|8C5|8C4|1|6804|6805||Interrupt vector Soft scroll control register (note 4)

|8C6-8C78C5|1|26805||-||unused Interrupt vector (0note 4)

|8C88C6-8CF8C7|2|8||6808-680f||Analogue input channels unused (0-7 (note 5)

|8D08C8-8DB8CF|8|3*4||6C006808-6C0B680f||Sound DMA channel attributes Analogue input channels 0-2 (see below) 7 (note 65)

|8DC8D0-8DE|8DB|3*4|6C00-6C0B|Sound DMA channel attributes 0-||unused 2 (0see below) (note 6)

|8DF8DC-8DE|3|1-||6C0F||DMA Control/Status unused (note 40)

|8E0-8F48DF|1|3*7||Internal|6C0F|DMA channel 0-2 internal registers (see below) Control/Status (note 74)

|8F5||18E0-8F4|3*7|Internal||gate array A0 register value DMA channel 0-2 internal registers (see below) (note 87)

|8F6|8F5|1||Internal||gate array A0 lock: 0=locked, 1=unlocked register value (note 98)

|8F7|8F6|1||Internal||ASIC unlock sequence state gate array A0 lock: 0=locked, 1=unlocked (note 109)

=== Notes ===

1. The sprite data is packed, with two sprite pixels per byte. Bits 7..4 define the first pixel and bits 3..0 define the second pixel.

2. The attributes for each sprite take 8 bytes. Each attribute block has the following format:

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Length''||''Description''

|0''Offset (Hex)''|''Length''|2||Sprite X (see note)''Description''

|2|0|2||Sprite Y X (see note)

|4||12|2|Sprite Magnification Y (see note)

|5-74|1|3||unused Sprite Magnification (0see note)

Note: the Sprite X, Y and magnification are in the same order as the ASIC registers

3. This is a direct copy of the palette in CPC+ ASIC Ram. There are 32 colours each with 2-bytes per colour.

4. These bytes in the snapshot represent the last value written to these ASIC registers.

5. These bytes represent the inputs to the analogue channels.

6. The attributes for each DMA channel take 4 bytes. Each attribute block has the following format:

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Length''||''Description''

|0''Offset (Hex)''|''Length''|2||DMA Channel address (see note)''Description''

| 0|2||1||DMA Channel prescalar address (see note)

|3|2|1||unused DMA Channel prescalar (0see note)

Note: the DMA address and prescalar are in the same order as the ASIC registers.

7 These registers are internal to the CPC+ and define the current DMA operation:

{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Length''||''Description''

|0''Offset (Hex)''|''Length''|2||loop counter (note a)''Description''

|2|0|2||loop address counter (note ba)

|4|2|2||pause count loop address (note cb)

|6||14|2|pause prescalar count (note dc)

a. This value represents the number of loops remaining. 0 = none. This count is between 0..0FFF. This counter counts down. b. This is the Amstrad memory address to loop back to. It is a pointer to the DMA instruction after the last REPEAT instruction.

cb. This value represents the pause count and the count is between 0the Amstrad memory address to loop back to.It is a pointer to the DMA instruction after the last REPEAT instruction..0FFF. (TO BE CHECKED: down counter? what exactly does it represent)

dc. This value represents the pause prescalar count and the count is between 0..FF.0FFF. (TO BE CHECKED: down counter? what exactly does it represent)

<br> 8. This value represents the last value written to this I/O port.

9. This value represents the lock status of the ASIC. If the ASIC is un-locked then the advanced features and ASIC registers are accessible.

10. This value represents the current unlock sequence state.

{|{{Prettytable|width: 700px; font-size: 2em;}}|''State ID''||''Synchronised State''||''Note''

|0''State ID''|''Synchronised State''|Not synchronised||ASIC is waiting for first non-zero byte to be written, this is the first synchronisation byte required''Note''

|1|0|Not synchronised||ASIC is waiting for first non-zero byte to be written, this is the second first synchronisation byte required

|2..10|1|Not synchronised||ASIC is waiting for zero byte from unlock sequence. e.g. if "2"to be written, ASIC this is waiting for &FF, the first byte of the unlock sequence. if "3" ASIC is waiting for &77, the second synchronisation byte of the unlock sequence.required