===Interrupt service(Vectored interrupts)===
The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels. The ASIC will always supply a vector which can be used by the CPU in interrupt modes 0 and 2 or ignored in interrupt mode 1.
Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 The top 5 bits of the DCSR are set if interrupts vector will be supplied from sound channels 0bit D7-2 respectively are active. For compatibility with earlier models, the raster interrupt is reset either by D3 of a CPU memory mapped interrupt acknowledge cyclevector register (IVR) at address 6805h in the ASIC, or by writing a 1 to bit D4 and the next two bits will determine the source of the mode and ROM enable registerinterrupt. The sound channel interrupts are cleared Bit D0 of the vector supplied is ignored by writing a 1 to the relevant bit Z80 in the DCSRinterrupt mode 2, but may be used in interrupt mode 0 (???).
<pre>
D2 D1
0 0 DMA channel 2 interrupt vector
0 1 DMA channel 1 interrupt vector
1 0 DMA channel 0 interrupt vector
1 1 Raster interrupt vector
</pre>
The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared, but has no effect on the vector itself (???). The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should always set up the IVR before placing the CPU in vectored interrupt mode.
The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.
Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the DCSR are set if interrupts from sound channels 0-2 respectively are active. These bits can be ignored by software which uses vectored interrupts where the DMA interrupts are automatically cleared, or by software which does not use the DMA channel interrupt facility. If DMA channel interrupts are used and not automatically cleared, they must be acknowledged by writing a “1” to the relevant DCSR bit. If bit D0 of the IVR is set to 0 bits D4-D6 of the DCSR will be cleared before the CPU gets a chance to read them.
Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.
Failure to observe this requirement may result in raster interrupts being missed. DMA Software which uses interrupts from expansion cards must be acknowledged by writing a "always use Z80 non-vectored interrupt mode 1" to , because the relevant DCSR bitexpansion bus does not support vectored interrupts. To summarize, vectored software should place a valid vector (D0 = 0) into the IVR. The hardware will supply a different vector for each interrupt source, and all interrupts are acknowledge automatically.
Non vectored software must write a "1" to bit D0 of the IVR, or leave it in it's reset state. Interrupt service software must examine bit D7 of the DCSR first, followed by bits D4-D6 (in any sequence) to identify the interrupt source. DMA interrupts must be acknowledged by writing a "1" to the relevant DCSR bit.
===Enhanced ROM cartridge support===