If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even IBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.
==== Border byte precision ====
This behaviour exhibited by CRTCs 0/2 shows that, despite their 1MHz clock speed, they can change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.