The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.
=== Video signals = Signal delay ====
There is a 1us delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.