Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
An interruption occurs at the end of an HSYNC. But on CRTCs 3/4, the HSYNC occurs HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means the interruption occurs 1µs later too.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions: