The DMA control and status register DCSR (at address 6C0Fh) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
* Bits2..0 are the channel enable bits. When set to "1" it enables the corresponding DMA channel. It can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on restreset.
* Bits7..4 are the interrupt bits. An interrupt bit is set to "0" when the corresponding channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is active at "0" if at least one of the interrupt bits is "0".