During an HSYNC, if HSYNC width (R3l) is changed with a value less than the current HSC, then HSC is overflowing. The only exception is for CRTC 1 with a value of 0, which cancels the current HSYNC.
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=== Overflow during Vertical Adjustment ===
* on CRTCs 0/1/2, VTAC overflows and continues to count up to 0 to reach new R5 value
* on CRTC 3/4, the line is considered the last and additional management ends
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=== Horizontal and Vertical Sync (R3) ===