*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
== CSYNC signal ==
On CPC, the HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified and merged by the Gate Array into a single CSYNC signal that will be sent to the display.