==== Z80: Some bad instruction timing analysis ====
Based on [[http://www.winape.net/ WinAPE>download>Plus test>plustest.dsk]] testbench, mapped using [[http://clrhome.org/table/ Z80 instruction set - ClrHome]], instruction described then in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]], against [[http://www.winape.net/ WinAPE]] passing testbench timing.
{| class="wikitable"
|-
! Hex !! Inst !! CPC timing !! MEM_wr:quick !! MEM_wr:slow !! remark
|-
| 02 || LD (BC), A || 2 || || 3 || Fixed on r005.8.16c3
|-
| 10 || DJNZ, e || 4/3 || 4/2 || 4/2 || T States begin by "(5, " : M1 is longer than 4.
Seems adding also one Wait_n in this case (as about MEM_wr)
|-
| 12 || LD (DE), A || 2 || || 3 || Fixed on r005.8.16c3
|-
| 22 || LD (nn), HL || 5 || 4 || 6 || Fixed on r005.8.16c3
|-
| 2A || LD HL, (nn) || 5 || 4 || 4 || MEM_WR not used by here,
it seems correct following doc : 4+3+3+3+3=16, 16/4=4.
Damn.
|-
| 32 || LD (nn), A || 4 || || 5 || Fixed on r005.8.16c3
|-
| 34 || INC (HL) || 3 || || 4 || Fixed on r005.8.16c3
|-
| 35 || || 3 || || 4 || Fixed on r005.8.16c3
|-
| 36 || || 3 || || 4 || Fixed on r005.8.16c3
|-
| 70 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| 71 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| 72 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| 73 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| 74 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| 75 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| 77 || || 2 || || 3 || Fixed on r005.8.16c3
|-
| C0 || RET nz || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET z.
|-
| C4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3
|-
| C5 || PUSH bc || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wr:low
|-
| C7 || RST 00h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3. T States begin by "(5, " : M1 is longer than 4.
|-
| C8 || RET z || 4/2 || 3/2 || 3/2 || RET cc, it seems correct following doc: true@5+3+3=>3*4; false@5=>2*4.
T States begin by "(5, " : M1 is longer than 4.
|-
| CC || || 5/3 || 5/3 || 6/3 || Fixed on r005.8.16c3
|-
| CD || || 5 || || 6 || Fixed on r005.8.16c3
|-
| CF || RST 08h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
|-
| D0 || RET nc || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET c.
|-
| D4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3
|-
| D5|| PUSH de || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wr:low
|-
| D7 || RST 10h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
|-
| D8 || RET c || 4/2 || 3/2 || 3/2 || RET cc
|-
| DC || || 5/3 || || 6/3 || Fixed on r005.8.16c3
|-
| DF || RST 18h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
|-
| E0 || RET po || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET pe.
|-
| E3 || || 6 || 5 || 6 || Fixed on r005.8.16c3
|-
| E4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3
|-
| E5 || PUSH hl || 4 || 3 || PUSH qq (same as F5), ok using MEM_wr:low
|-
| E7 || RST 20h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
|-
| E8 || RET pe || 4/2 || 3/2 || 3/2 || RET cc
|-
| EC || || 5/3 || || 6/3 || Fixed on r005.8.16c3
|-
| EF || RST 28h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
|-
| F0 || RET p || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET m.
|-
| F4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3
|-
| F5 || PUSH af || 4 || 3 || || PUSH qq, 5+3+3=11<3*4, is MEM_WR prologation effective two times here 1T+1T?
yes: pushing a register pair here, ok using MEM_wr:low
|-
| F7 || RST 30h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
|-
| F8 || RET m || 4/2 || 3/2 || 3/2 || RET cc
|-
| FC || || 5/3 || || 6/3 || Fixed on r005.8.16c3
|-
| FF || RST 38h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3.
|-
|}
CC codes : all ok DD codes : somes ko ED codes : somes ko FD codes : somes ko DD CB codes : all ko FD CB codes : all ko Solved in r005.8.16c4 results :[[File:FPGAmstrad plustest5 r00516.8.16c4 part1.png|thumbnail|FPGAmstrad_plustest5_r005.8.16c4_part1]][[File:FPGAmstrad plustest5 r005.8.16c4 part2.png|thumbnail|FPGAmstrad_plustest5_r005.8.16c4_part2]] r005.8.16c6 results :[[File:FPGAmstrad plustest5 r005.8.16c6 part1.png|thumbnail|FPGAmstrad_plustest5_r005.8.16c6_part1]][[File:FPGAmstrad plustest5 r005.8.16c6 part2.png|thumbnail|FPGAmstrad_plustest5_r005.83 by Sorgelig.16c6_part2]]
==== Z80: Some bad instruction analysis ====
Based on [[https://cpcrulez.fr/applications_CPM-util-zexall.htm Zexall: Z80 instruction set exerciser]], running fine in JavaCPC.
Solved in r005.8.16.3 by Sorgelig.
==== Z80: ED A9 cpd(r) / ED A1 cpi(r) ====
Problem here : CPDR and CPIR has same implementation than CPD and CPI.