VHDL (very high-level description language)
This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw then and translate then into VHDL)
Its syntax does look like ADA language. It differs from computer langage as its first instruction does generaly look like :
if rising_edge(clock) then output_wire <= input_wire xor 1; end if;
All instruction are runs at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it the time between the action is launched and then take effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.
You can also have local registered value, using affectation operator ":=", without delta-time (at once) :
output_wire_mem := input_wire xor 1; output_wire_mem := output_wire_mem xor 1; output_wire <= output_wire_mem;
VHDL can be synthetised (compiled) into FPGA chip. Two families of FPGA chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them... VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug them components together using drawn schematics.
IDE :
- Xilinx webpack
- Quartus web edition
Development starter-kit :
Final platform (can be also used to develop) :
- FPGAmstrad on MiST-board
- Amedia Computer - fr
Books :
- Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
- VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé