8251 USART chip

Control Register (W)

The first write after internal or external Reset is the "Mode Instruction":

 Bit  Expl.
 0-1  Baud Rate Divider     (0=Sync Mode, 1=Div1, 2=Div16, 3=Div64)
 2-3  Character Length      (0=5bit, 1=6bit, 2=7bit, 3=8bit)
 4    Parity Enable         (0=Disable, 1=Enable)
 5    Parity Type           (0=Odd, 1=Even)
 In Async mode:
 6-7  Stop Bits             (0=Reserved, 1=1bit, 2=1.5bit, 3=2bit)
 In Sync mode:
 6    External Sync Detect  (0=Syndet is an output, 1=Syndet is an input)
 7    Single Character Sync (0=Double Character, 1=Single Character)

If (only if) the above 1st write selected Sync Mode, then 2nd/3rd write are:

 2nd write - Sync Character 1
 3rd write - Sync Character 2

All further writes to the Control Register are "Command Instructions":

 Bit  Expl.
 0    Transmit Enable      (0=Disable, 1=Enable)
 1    Data Terminal Ready  (0=No, 1=Yes) (DTR Pin)
 2    Receive Enable       (0=Disable, 1=Enable)
 3    Send Break Character (0=Normal, 1=Force TxD "low")
 4    Error Reset          (0=No change, 1=Reset Error Flags)
 5    Request to Send      (0=No, 1=Yes) (RTS Pin)
 6    Internal Reset       (0=No change, 1=Reset; expect new Mode Instruction)
 7    Enter Hunt Mode      (0=No, 1=Search Sync Characters; Sync Mode only)

Status Register (R)

 Bit  Expl.
 0    Transmit Ready       (0=Busy, 1=Ready; "DB Buffer Empty")
 1    Receive Ready
 2    Transmit Empty
 3    Parity Error
 4    Overrun Error
 5    Framing Error
 6    Syndet/Brkdet
 7    Data Set Ready (DSR Pin)

Data Register (R/W)

 Bit  Expl.
 0-7  Data

Aleste 520EX

Used by Aleste 520EX (a CPC clone with built-in RS232 interface):

 EEXXh  Aleste - 8251 USART chip (RS232/Mouse) Data (R/W)
 EFXXh  Aleste - 8251 USART chip (RS232/Mouse) Control/Status (R/W)
 Uses a KR580WW51A (russian clone of the 8251).
 Clock source comes from a 8253 chip.

MHT Ingenieros RS232 para Amstrad

Used by RS-232 para Amstrad from MHT Ingenieros, mapped to Ports:

 FADCh - MHT RS232 - 8251 USART data
 FADDh - MHT RS232 - 8251 USART control/status
 Clock source comes from a 8253 chip.

Schneiderware V/24 Interface

Used by Schneiderware V/24 Interface from CPC Schneider International, mapped to Ports:

 F9E0h (or F9E2h) Schneiderware V/24 8251 USART chip Data 
 F9E1h (or F9E3h) Schneiderware V/24 8251 USART chip Control
 Clock source comes from a 8253 chip.
 Clock input to that chip is jumper-selectable: 2MHz (default), or 1MHz.
 Caution: The RTS/CTS and DSR/DTR handshaking signals are disabled by
 default (via jumpers) (and, in worst case, also by additional inaccesible
 hardwired connections, hidden underneath of the jumpers)

Cirkit Serial Interface

Used by Cirkit serial interface (for use with the included Prestel Link modem)):

 FADFh - Cirkit - 8251 UART Data register
 FBDFh - Cirkit - 8251 UART Status/Control register
 TX clock source is fixed (19.2KHz), RX clock source can be selected via DTR bit (1200Hz or 19.2KHz).

The original 8251 seems to be very rare (there's no programming info found in the internet). The 8251A is backwards compatible, but includes some additional features. The 8251A gives some details on the additional features, so one could eventually use the 8251A datasheet to reconstruct the functionality of the original 8251.

However, since the 8251 is so rare, it's rather doubtful that the Aleste or Circit actually uses these chips, they probably use 8251A chips.

• The Circit advert says 8251 (which is maybe meant to be an abbreviation for 8251A).
• Russian to Western part number translation tables say KR580WW51A is 8251 (probably an abbreviation for 8251A, too) (especially as the ending "A" in "KR580WW51A" implies that it is an 8251A).

• Media:8251A.pdf - newer 8251A datasheet (detailed info)
• Media:8251.pdf - older 8251 datasheet (pin-out only, without programming info)