The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate).
Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest.
- Bryce, my interpretation in Note 2 is EXACTLY the same as what you are saying. It maps to ALL four addresses.
- Thus, the decoding of the "lower" two addressbits (A2,A3) is total nonsense, really. --Nocash 19:15, 10 May 2010 (UTC)
Yes, it maps all four addresses as you state correctly, just the bit about calling it non-sense is what I disagree with - If any of the four addresses are selected, the output of the 74LS20 activates the Chip Select on the STI and then in combination with the connections to pins 32-35 on the STI allows that each register can be individually addressed by the amstrad. How else would you achieve this without the configuration shown in the schematic? What signal should activate the STI CS pin, if not this one? How would you do it?
Bryce.