Upper ROM Bank Number

Writing to Port DFxxh selects the Upper ROM Bank Number (in range of 00h..FFh) to be mapped to memory at C000h..FFFFh. Whether or not the ROM is enabled (or if RAM is mapped to that region) is controlled by the Gate Array.

The ROM Bank Number is not stored anywhere inside of the CPC. Instead, peripherals must watch the bus for writes to Port DFxxh, check if the Bank Number matches the Number where they want to map their ROM to, and memorize the result by setting/clearing a flipflop accordingly (eg. a 74LS74).

If the flipflop indicates a match, and the CPC outputs A15=HIGH (upper memory half), then the peripheral should set /OE=LOW (on its own ROM chip), and output the opposite level, ROMDIS=HIGH to the CPC (disable the CPC's BASIC ROM).

Additionally the CPC's /ROMEN should be wired to peripheral ROM chip's /CS pin. A14 doesn't need to be decoded since there is no ROM at 8000h..BFFFh, only at C000h..FFFFh.

By default, if there are no peripherals issuing ROMDIS=HIGH, then BASIC is mapped to all ROM banks in range of 00h..FFh.

 00h  BASIC (or AMSDOS, depending on LK1)
 07h  AMSDOS (or BASIC, depending on LK1)
 00h..07h  Bootable ROMs on CPC 464/664/6128 (KL_ROM_WALK)
 08h..0Fh  Bootable ROMs on CPC 664/6128 (KL_ROM_WALK)
 10h..FFh  Non-bootable ROMs (or secondary banks of Bootable ROMs)
 FCh..FFh  Can be used, but aren't accessible by BIOS functions
 FFh  BASIC (or ROM with similar ID; for the crude 128K RAM-size detection in CP/M+)

• You may want to add a list of devices with ROM here, please also include their fixed bank number(s), or selectable range of bank number(s))
• Not sure if there are devices with incompletely decoded bank numbers? Eg. a ROM mapped to bank 06h, but also mirrored to 16h, 26h, 36h, etc. If so, these addresses should be listed here, too.