Revision as of 15:11, 23 December 2016

Snapshot (.SNA) file format

The format was first defined for the CPCEMU emulator but is now widely supported. The format was originally defined by Marco Vieth. Version 3 was defined by Ulrich Doewich, Martin Korth, Richard Wilson and Kevin Thacker.

There are 3 versions defined in this document. Version 3 is the most recent and is currently supported by a few of the most recent emulators.

Snapshots produced with CPCE appears to be the most compatible and will run correctly using any emulator.

Abbreviations:

• GA = "Gate Array"
• CRTC = "6845 Cathode Ray Tube Controller"
• PPI = "Intel 8255 Programmable Peripheral Interface"
• PSG = "AY-3-8912 Programmable Sound Generator"

Version 1

Notes

1. All multi-byte values are stored in little-endian format (low byte followed by higher bytes).

2. "IFF0" reflects the state of the maskable interrupt (INT). "IFF1" is used to store the state of IFF0 when a non-maskable interrupt (NMI) is executed. Bit 0 of these bytes is significant. For CPCEMU compatibility, these bytes should be set to "1" when the IFF flip-flop is "1" and "0" when the flip-flop is "0". For compatibility with other emulators, bits 7-1 should be set to "0". When bit 0 of "IFF0" is "0" maskable interrupts will be ignored. When bit 0 of "IFF1" is "1" maskable interrupts will be acknowledged and executed. See the document about the Z80 for more information.

3. This byte will be 0, 1 or 2 for the interrupt modes 0, 1 or 2. The interrupt mode is set using the "IM x" instructions. See the document about the Z80 for more information.

4. These registers are from the alternate register set of the Z80.

5. These registers are 16-bit. "low" indicates bits 7..0, "high"indicates bits 15..8.

6. This byte represents the inputs to PPI port A regardless of the input/output setting of this port.

7. This byte represents the inputs to PPI port B regardless of the input/output setting of this port.

8. This byte represents the outputs from port C regardless of the input/output setting of this port.

9. This byte represents the PPI control byte which defines the input/output and mode of each port and not the last value written to this port. For CPCEMU compatibility bit 7 of this byte must be set to "1".

10. This byte in the snapshot represents the selected pen register of the Gate-Array. This byte is the last value written to this port. Bit 7,6,5 should be set to "0".

11. This byte in the snapshot represents the multi-configuration register of the Gate-Array. This byte is the last byte written to this register. For CPCEMU compatibility, bit 7 should be set to "1" and bit 6 and bit 5 set to "0".

12. These bytes are the current palette. For CPCEMU compatibility, these bytes should have bit 7=bit 6=bit 5="0". Bits 4..0 define the colour using the hardware colour code. The colours are stored in the order pen 0, pen1, pen 2,...,pen 15 followed by border colour.

13. This byte represents a ram configuration for a Dk'Tronics/Dobbertin/Amstrad compatible RAM expansion, or the built in RAM expansion of the CPC6128 and CPC6128+. Bits 5..0 define the ram expansion code. For CPCEMU compatibility, bit 7 and bit 6 of this byte should be set to "0".

14. This byte in the snapshot represents the index of the currently selected CRTC register. For compatibility with CPCEMU this value should be in the range 0-31.

15. These bytes represent the data of the CRTC's registers.

16. This byte in the snapshot represents the last byte written to the "ROM select" I/O port.

17. This byte in the snapshot represents the index of the currently selected PSG register. For CPCEMU compatibility, this byte should be in the range 0-15.

18. the memory dump can have size 0 in version 3 and in this case all RAM is described in additional blocks (MEM0-MEM8). If a memory dump has a non-zero size, then it is uncompressed and describes the main 64KB ram immediately followed by the second 64KB ram (if present) (this ram is inside 128KB machines or machines with 64KB from a Dk'Tronics/Dobbertin/Amstrad compatible RAM expansion. Note that CPCEMU can only write a 64K or 128K snapshot.

Changes and additions in Version 2 from Version 1

Notes

1. If standard CPC raster interrupts are used, interrupts are acknowledged and "executed" at the time they are requested, then there will be 6 interrupts executed per screen update cycle.

• CPCEMU uses a simple system to emulate the interrupts. It is assumed there are exactly 6 interrupts per screen update cycle (the interrupts are assumed to occur at a frequency of 300Hz). This byte records the interrupt number in the current screen update cycle. More accurate emulators use the correct interrupt generation method and may ignore this byte. For CPCEMU compatibility, these emulators should set this byte to "0".

• CPCEMU uses a simple system to emulate the screen display. It allows the mode to be changed in each of the 6 interrupts that occur during a single 50Hz/60Hz period. These bytes represent the mode in each of these sections, i.e. the screen modes (0,1 or 2) for the interrupts 0..5. More accurate emulators support changing of the screen mode at any point supported by the Amstrad hardware, these emulators should write "0" for all these bytes.

2. A version 2 snapshot can describe up to 512KB of Dk'Tronics compatible RAM in addition to the 64KB base ram. However, the RAM *MUST* be continuous, therefore it's limited to 64KB, 256KB or 512KB additional RAM. The Dk'Tronics silicon disk can't be described on it's own because it's RAM configurations do not start at C4.

The following configurations can be described:

• 64KB base + 64KB extra RAM (e.g. Dk'Tronics 64KB RAM Expansion)
• 64KB base + 256KB extra RAM (e.g. Dk'Tronics 256KB RAM Expansion)
• 64KB base + 512KB extra RAM (e.g. Dk'Tronics 256KB RAM Expansion & Dk'Tronics 256KB Silicon Disk OR X-MEM OR Symbiface 2 OR other device which provides 512KB)

Changes and additions in Version 3 from Version 2

Notes

1. This byte in the snapshot represents the last byte written to the printer I/O port (this byte does not include the automatic inversion of the strobe caused by the Amstrad hardware).

2. This register is internal to the CRTC and counts the number of character-lines. The counter counts up. This value is in the range 0-127. (This counter is compared against CRTC register 4).

3. This register is internal to the CRTC and counts the number of raster-lines. The counter counts up. This value is in the range 0-31. (This counter is compared against CRTC register 9).

4. This register is internal to the CRTC and counts the number of raster-lines during vertical adjust. The counter counts up. This value is in the range 0-31. This should be ignored if the CRTC is not "executing" vertical. adjust.(This counter is compared against CRTC register 5).

5. This register is internal to the CRTC and counts the number of characters during horizontal sync. This counter counts up. This value is in the range 0-16. This should be ignored if the CRTC is not "executing" horizontal sync. (This counter is compared against CRTC register 3).

6. This register is internal to the CRTC and counts the number of scan-lines during vertical sync. This counter counts up. This value is in the range 0-16. This should be ignored if the CRTC is not "executing" vertical sync. (This counter is compared against CRTC register 3).

7. These bytes define the internal state of the CRTC. Each bit in these bytes represents a state.

8. When VSYNC is active, the CRTC is "executing" vertical sync, and the vertical sync width counter in the snapshot is used.

9. When HSYNC is active, the CRTC is "executing" horizontal sync width counter in the snapshot is used.

10. When Vertical total adjust is active, the CRTC is "executing" vertical total adjust and the vertical total adjust counter in the snapshot is used.

11. This register is internal to the CRTC and counts the number of characters. This counter counts up. This value is in the range 0-255. (This counter is compared against CRTC register 0).

12. This counter is internal to the GA and counts the number of HSYNCs. This counter is used to generate CPC raster interrupts. This counter counts up. This value is in the range 0-51.

13. This flag is "1" if a interrupt request has been sent to the Z80 and it has not yet been acknowledged by the Z80. (A interrupt request is sent by the GA for standard CPC raster interrupts or by the ASIC for raster or dma interrupts).

14. This is a counter internal to the GA and counts the number of HSYNCs since the start of the VSYNC and it is used to reset the interrupt counter to synchronise interrupts with the VSYNC. This counter counts up. This value is between 0 and 2. If this value is 0, the counter is inactive. If this counter is 1 or 2 the counter is active.

15. This is the current cylinder for each of 4 drives.

16. In WinAPE this counter is reset if a VSYNC occurs which causes the monitor to retrace vertically. This occurs if the VSYNC signal is active and this counter is greater than a threshold set by the V-Hold (normally 295 when V-Hold is 0), or if the counter reaches the maximum value (normally 351 when V-Hold is 0).

17. Since Plus emulation requires more information than simply whether an interrupt is active, this value (as used internally by WinAPE) contains:

• Bit 7 - Gate Array (or PRI) interrupt.
• Bit 6 - DMA Channel 0 interrupt.
• Bit 5 - DMA Channel 1 interrupt.
• Bit 4 - DMA Channel 2 interrupt.

It can be a combination of all or any interrupt sources. Interrupts are executed in the order raster, DMA 2, DMA 1, DMA 0.

Immediately following the memory dump there is optional data which is separated into chunks.

Each chunk of data has a header and this is followed by the data in the chunk. The header has the following format:

Notes:

1. The chunks are defined with 4-byte character codes. (e.g. "CPC+"). In this example, the 4-byte character code would be stored in the file as 'C' then 'P' then 'C' then '+'.

2. The "Chunk data length" defines the length of data following the header and does not include the size of the header. This number is stored in little endian format.

3. If a emulator finds a chunk which it does not support then it should skip the chunk and continue with the next chunk in the file. Therefore an emulator author may add emulator specific chunks to the file and it will not prevent the snapshot from being used with other emulators that do not recognise the added chunks.

4. There is not a terminator chunk. The snapshot reader should determine if there are more chunks based on the size of data remaining to be read from the file.

The following chunks are currently defined:

DSCA,DSCB (Winape)

The DSCA block contains the filename of the disc image inserted into drive A. The filename is stored as 8-bit ASCII (any Unicode characters with codes 0x100 or above will be translated to ? and therefore filenames with these characters can't be stored in Snapshots). The length of the block is the length of the filename in bytes.

DSCB is similar to DSCA but stores the filename of the disc image inserted into drive B.

This option must be enabled in Winape for this chunk to be saved.

ROMS (Winape)

This block contains a list of filenames for each ROM (and cartridge) that is defined in Winape. The length of the block is the length for all strings.

If a ROM is not defined, a single NUL (0) byte is present, otherwise there is a null terminated 8-bit ASCII string.

First in the list is the filename (or internal name) for the cartridge (prefixed with a 'A' character), followed by lower rom and then upper roms 0-32.

Internal ROMs are listed by their internal name (the name listed in the drop down when you configure the roms) (e.g. OS464).

This option must be enabled in Winape for this chunk to be saved.

NOTE: The selected Multiface ROM is not saved in the snapshot.

MEM0-8 Chunk

The MEM0-8 chunks contain at most 64KB of data. The data may be compressed or stored uncompressed. If the size is exactly 65536 bytes the data is uncompressed, otherwise it is compressed. Up to 512KB additional RAM can be stored in a snapshot.

The compression scheme is RLE with 0x0e5 as the control byte.

Data is encoded as:

• <byte> for a single occurrence of a byte (not 0x0e5) (e.g. 0x013)
• 0x0e5,<count>,<byte> for multiple occurances of a byte (e. 0x0e5,0x04,0x013 for 0x013 repeated 4 times)
• 0x0e5,0 for a single 0x0e5 byte (e.g. 0x0e5)

The blocks are:

• MEM0 - main 64KB ram
• MEM1 - c4,c5,c6,c7 configurations (extra 64KB ram in 128KB machines) (256KB Dk'Tronics RAM, X-MEM)
• MEM2 - cc,cd,ce,cf configurations (256KB Dk'Tronics RAM, X-MEM)
• MEM3 - d4,d5,d6,d7 configurations (256KB Dk'Tronics RAM, X-MEM)
• MEM4 - dc,dd,de,df configurations (256KB Dk'Tronics RAM, X-MEM)
• MEM5 - e4,e5,e6,e7 configurations (256KB Dk'Tronics Silicon Disk, X-MEM)
• MEM6 - ec,ed,ee,ef configurations (256KB Dk'Tronics Silicon Disk, X-MEM)
• MEM7 - f4,f5,f6,f7 configurations (256KB Dk'Tronics Silicon Disk, X-MEM)
• MEM8 - fc,fd,fe,ff configurations (256KB Dk'Tronics Silicon Disk, X-MEM)

NOTE:

1. A snapshot may contain a mix of "standard" memory data (e.g. the data follows the header and is uncompressed) and additional MEM blocks as required.

2. If the snapshot is not compressed, then up to 128KB will be stored as "standard" memory data, the additional RAM stored in MEM2-MEM8 blocks.

3. If the snapshot is compressed, then the "standard" memory data will have 0 size and there will be a MEM0 in addition to the additional memory blocks.

4. Version 3 doesn't require memory to be continuous. A Dk'tronics silicon disk on it's own can be described with this version.

5. Winape allows a 4MB RAM expansion to be enabled but doesn't save the additional RAM in the snapshot.

CPC+ Chunk

Notes

1. The sprite data is packed, with two sprite pixels per byte. Bits 7..4 define the first pixel and bits 3..0 define the second pixel.

2. The attributes for each sprite take 8 bytes. Each attribute block has the following format:

Note: the Sprite X, Y and magnification are in the same order as the ASIC registers

3. This is a direct copy of the palette in CPC+ ASIC Ram. There are 32 colours each with 2-bytes per colour.

4. These bytes in the snapshot represent the last value written to these ASIC registers.

5. These bytes represent the inputs to the analogue channels.

6. The attributes for each DMA channel take 4 bytes. Each attribute block has the following format:

Note: the DMA address and prescalar are in the same order as the ASIC registers.

7 These registers are internal to the CPC+ and define the current DMA operation:

a. This value represents the number of loops remaining. 0 = none. This count is between 0..0FFF. This counter counts down.

b. This is the Amstrad memory address to loop back to. It is a pointer to the DMA instruction after the last REPEAT instruction.

c. This value represents the pause count and the count is between 0...0FFF. (TO BE CHECKED: down counter? what exactly does it represent)

d. This value represents the pause prescalar count and the count is between 0..FF. (TO BE CHECKED: down counter? what exactly does it represent)

8. This value represents the last value written to this I/O port.

9. This value represents the lock status of the ASIC. If the ASIC is un-locked then the advanced features and ASIC registers are accessible.

10. This value represents the current unlock sequence state.