Difference between revisions of "C't 512 KB internal RAM expansion"

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A project to upgrade a CPC6128 to 512K RAM (total), done by replacing the CPC6128's RAM chips, and its PAL banking chip, the project was released 1987 in german magazine ''c't Magazin''.
 
A project to upgrade a CPC6128 to 512K RAM (total), done by replacing the CPC6128's RAM chips, and its PAL banking chip, the project was released 1987 in german magazine ''c't Magazin''.
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== Technical ==
 
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The memory is accessed via Port 7Fxxh, as on [[Standard Memory Expansions]]. Since the internal RAM is removed, its total capacity is only 512K (unlike standard 512K expansions which provide 64K internal plus 512K external memory, ie. 576K total). Altogether, the c't expansion works like a 448K dk'tronics expansion (leaving the banks selected via OUT [7Fxxh],FCh..FFh unused).
 
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One half (256K) of the total (512K) expansion memory can be accessed as Video RAM (with normal expansions, only 64 KB are accessible as VRAM). This is making the expansion slightly incompatible with the dk'tronics standard. However, usually expansion memory is mapped to 4000h-7FFFh, whilst VRAM is usually mapped to C000h-FFFFh. So, most existing software may work with it, without accidently displaying garbage on the screen.
 
  
 
== The Circuit ==
 
== The Circuit ==
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* RAMDIS is not supported, not a problem in most cases, but won't work with some special types of expansion hardware, like [[Multiface II]].
 
* RAMDIS is not supported, not a problem in most cases, but won't work with some special types of expansion hardware, like [[Multiface II]].
 
* The bank selection for CPU address 4000h..7FFFh does also affect bank bits0-1 for VRAM at 4000h..7FFFh; thus the CRTC may see bank 0-3 in that region (whilst, as far as known, on a normal CPC, it should always see bank 1 in that region).
 
* The bank selection for CPU address 4000h..7FFFh does also affect bank bits0-1 for VRAM at 4000h..7FFFh; thus the CRTC may see bank 0-3 in that region (whilst, as far as known, on a normal CPC, it should always see bank 1 in that region).
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** '''Notice''' the included sample program '''does''' seem to map VRAM to 4000h, whilst mapping expansion banks to 4000h at the same time. Theoretically, this should result in display glitches - unknown if/how/why the sample works [?]
  
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== Missing Info ==
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== Memory Configurations ==
  
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* Unknown which banks are usable as VRAM
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The memory is controlled by OUT [7Fxxh],C0h..DFh instructions. Values C0h..C7h are working same as on normal CPC6128s. Values C8h..DFh do access the additional RAM banks (C8h..D3h when using the cut-down 320K upgrade variant).
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** The first four 16K bank are (probably) usuable as VRAM (as on all 64K CPC models)
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** The next four 16K bank are (hopefully) not usuable as VRAM (for CP/M+ compatibility, which uses them as Work RAM)
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** For further banks it's totally unknown if they are used as VRAM or not
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* Unknown if it's fully dk'tronics compatible, or more like incompletely implemented Inicron variant
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* Unknown what happens on accessing the unused region via OUT [7Fxxh],FCh..FFh
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== Memory Configurations ==
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   OUT [7Fxxh],C0h+...  0  1  2  3    4  5  6  7    8..31
 
   OUT [7Fxxh],C0h+...  0  1  2  3    4  5  6  7    8..31
Line 51: Line 39:
  
 
== PAL Source Code ==
 
== PAL Source Code ==
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Below is a typed-up and commented copy of the PALASM source code from the original article.
  
 
  D7D6 D0  D3  D4  D1  D2  NCAS A15  A14  GND  ;pin 1..10
 
  D7D6 D0  D3  D4  D1  D2  NCAS A15  A14  GND  ;pin 1..10
Line 85: Line 75:
 
   
 
   
 
  IF (GND) /IOWR=/IOWR      ;dummy (do not output anything on this pin)
 
  IF (GND) /IOWR=/IOWR      ;dummy (do not output anything on this pin)
 +
 +
Some notes on the syntax:
 +
* The first two lines assign the pin-outs. Observe that leading "/" slashes are omitted here. For example, "/CPU" (in schematic) becomes "CPU" (in source code). Accordingly "/CPU" (in source code) would be double-negated "//CPU" aka "CPU" (in schematic).
 +
* The "IF (condition) signal=" part means that "signal" becomes an output when condition is true. In the above source code, condition is always true (VCC), or, for the last 2 lines, always false (GND).
 +
* The "*" and "+" operators are meaning "* = AND", "+ = OR". The idea behind that confusing syntax was to make it "easier" to learn for people who are trained only in basic maths (the formulas do also work when treating *=multiply, and +=plus. For example: 1+0+1+1 = 3 = nonzero = true).
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* There must be some priority ordering in the formulas: Either * before +, or operations inside of a line before merging the results of the separate lines (in above examples, both ordering methods do work).
  
 
== Newer Info ==
 
== Newer Info ==

Revision as of 09:51, 8 May 2010

A project to upgrade a CPC6128 to 512K RAM (total), done by replacing the CPC6128's RAM chips, and its PAL banking chip, the project was released 1987 in german magazine c't Magazin.

The Circuit

  • DRAM Replacement - Replace the sixteen old 64Kx1 DRAM chips (IC119-IC134) by new 256Kx1 DRAMs. The chips have same pinouts, only pin 1 is changed (old: NC, new: A8 row:column address signal). Optionally, replace only bank 0 (IC127-IC134) for getting only 320K (256K+64K) instead of 512K total (2x256K).
  • PAL Replacement - Replace the old PAL (IC118) by the new daughterboard. Most signals connect to the PAL socket (green in schematic), a extra few wires connect elsewhere on mainboard (red), as an optional "bonus" feature, the circuit contains logic for a 3rd floppy drive (blue).

  • Schematic

  • PCB

Component List 

 16x 41256 (256Kx1 DRAM)   ;replacing the CPC6128's 16 built-in 64Kx1 DRAMs
  1x PAL 16L8              ;replacing the CPC6128's built-in PAL
  1x 74LS38                ;Quad 2-input NAND, OC
  1x 74LS273               ;8bit latch, of which only 5bit are used here
  1x 2200 Ohm resistor     ;pull-up for OC output
  1x 470 Ohm resistor      ;pull-up for OC output
  1x 47 Ohm resistor       ;purpose unknown (noise related? shortcut protection?)

Compatibility Problems

  • RAMDIS is not supported, not a problem in most cases, but won't work with some special types of expansion hardware, like Multiface II.
  • The bank selection for CPU address 4000h..7FFFh does also affect bank bits0-1 for VRAM at 4000h..7FFFh; thus the CRTC may see bank 0-3 in that region (whilst, as far as known, on a normal CPC, it should always see bank 1 in that region).
    • Notice the included sample program does seem to map VRAM to 4000h, whilst mapping expansion banks to 4000h at the same time. Theoretically, this should result in display glitches - unknown if/how/why the sample works [?]

Memory Configurations

The memory is controlled by OUT [7Fxxh],C0h..DFh instructions. Values C0h..C7h are working same as on normal CPC6128s. Values C8h..DFh do access the additional RAM banks (C8h..D3h when using the cut-down 320K upgrade variant). 

 OUT [7Fxxh],C0h+...   0  1  2  3    4  5  6  7    8..31
 -------------------------------------------------------
 Bank at C000h..FFFFh  3  7  7  7    3  3  3  3    7 (!)
 Bank at 8000h..BFFFh  2  2  6  2    2  2  2  2    2
 Bank at 4000h..7FFFh  1  1  5  3    4  5  6  7    8..31
 Bank at 0000h..3FFFh  0  0  4  0    0  0  0  0    0

PAL Source Code

Below is a typed-up and commented copy of the PALASM source code from the original article. 

D7D6 D0   D3   D4   D1   D2   NCAS A15  A14  GND  ;pin 1..10
CPU  A15S AMUX MUX  LCLK CAS1 CAS0 IOWR A14S VCC  ;pin 11..20

IF (VCC) /LCLK= D7D6 * /A15 * /IOWR               ;load external latch on OUT [7Fxxh],C0h..FFh

IF (VCC) /CAS0= /NCAS * /D4  +                    ;bank bit4=0, select bank 0..15 (CPU and CRTC)
         /CAS0= /NCAS *  A15 +
         /CAS0= /NCAS * /A14 +
         /CAS0= /NCAS *  CPU

IF (VCC) /CAS1= /NCAS * D4 * /A15 * A14 * /CPU    ;bank bit4=1, select bank 16..31 (CPU at 4000h..7FFFh only)

IF (VCC) /A14S= /A14             +                             ;bank bit0
                /D0  * D2 * /A15 +
                /D0  * D3 * /A15 +
                /D0  * D4 * /A15

IF (VCC) /A15S= /A14 *                    /A15 +               ;bank bit1
                /D1  *                    /A15 +
                /D4  * /D3  * /D2 * /D0 * /A15 +
                /D4  * /D3  * /D2 * /D1 * /A15

IF (VCC) /AMUX= /D0  *  D1  * /D2 * /D3 * /D4 * /CPU * /MUX +
                 A15 *  A14 * /D2 *  D0 *       /CPU * /MUX +
                 A15 *  A14 * /D2 *  D1 *       /CPU * /MUX +
                 A15 *  A14 *        D3 *       /CPU * /MUX +
                 A15 *  A14 *        D4 *       /CPU * /MUX +
                /A15 *  A14 *        D2 *       /CPU * /MUX +  ;bank bit2
                /A15 *  A14 *        D3 *       /CPU *  MUX    ;bank bit3

IF (GND) /MUX = /MUX      ;dummy (do not output anything on this pin)

IF (GND) /IOWR=/IOWR      ;dummy (do not output anything on this pin)

Some notes on the syntax:

  • The first two lines assign the pin-outs. Observe that leading "/" slashes are omitted here. For example, "/CPU" (in schematic) becomes "CPU" (in source code). Accordingly "/CPU" (in source code) would be double-negated "//CPU" aka "CPU" (in schematic).
  • The "IF (condition) signal=" part means that "signal" becomes an output when condition is true. In the above source code, condition is always true (VCC), or, for the last 2 lines, always false (GND).
  • The "*" and "+" operators are meaning "* = AND", "+ = OR". The idea behind that confusing syntax was to make it "easier" to learn for people who are trained only in basic maths (the formulas do also work when treating *=multiply, and +=plus. For example: 1+0+1+1 = 3 = nonzero = true).
  • There must be some priority ordering in the formulas: Either * before +, or operations inside of a line before merging the results of the separate lines (in above examples, both ordering methods do work).

Newer Info

Having a short look at the article, it seems to be all different as than expected:

  • There is no dk'tronics compatibility intended - however, c't and dk'tronics are based on the CPC6128 banking mechanism, so they work similar, and to some level there is some (unintended) compatibility. Namely, ONE HALF of the memory can be accessed in dk'tronics style fashion.
  • There seems to be no hardware based "Video RAM" support at all. However, there's some unspectacular software based example included that copies expansion RAM to VRAM via LDIR opcode.

Scanned Article / Schematics

Original names of the articles are: Aus David wird Goliath: 512 KB RAM für Schneider CPC (part 1), and Byte-Hirte: RAM-Disk-Treiber für des CPCs 512 Kbyte (part 2). Both articles are written by Gabor Herr and Hubert Schröer.

Related hardware modifications

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