Originally the CPC was destined to be designed around the 6502 processor. But when Amstrad approached [[Locomotive Software]] to develop a Basic for it with a very tight deadline, Locomotive PLC, who already had a Z80 Basic in the works, urged and convinced Amstrad to switch to the Z80.
== Opcode matrix for the 6502 instruction set ==
{| class="wikitable"
!colspan=13|
|-
|colspan=13| Addressing modes: <span style="background-color: #e0e0e0;">'''A''' - accumulator</span>, <span style="background-color: #e0ffe0;">'''#''' - immediate</span>, <span style="background-color: #ffe0e0;">'''zpg''' - zero page</span>, <span style="background-color: #e0ffff;">'''abs''' - absolute</span>, <span style="background-color: #ffe0ff;">'''ind''' - indirect</span>, '''X''' - indexed by X register, '''Y''' - indexed by Y register, <span style="background-color: #ffffe0;">'''rel''' - relative</span>
|-
!rowspan=2| High nibble ||colspan=12| Low nibble
|-
! 0|| 1|| 2|| 4|| 5|| 6|| 8|| 9|| A|| C|| D|| E
|-
! 0
| bgcolor=#e0e0e0|BRK
| bgcolor=#ffe0ff|ORA (''ind'',X)
|
|
| bgcolor=#ffe0e0|ORA ''zpg''
| bgcolor=#ffe0e0|ASL ''zpg''
| bgcolor=#e0e0e0|PHP
| bgcolor=#e0ffe0|ORA #
| bgcolor=#e0e0e0|ASL A
|
| bgcolor=#e0ffff|ORA ''abs''
| bgcolor=#e0ffff|ASL ''abs''
|-
! 1
| bgcolor=#ffffe0|BPL ''rel''
| bgcolor=#ffe0ff|ORA (''ind''),Y
|
|
| bgcolor=#ffe0e0|ORA ''zpg'',X
| bgcolor=#ffe0e0|ASL ''zpg'',X
| bgcolor=#e0e0e0|CLC
| bgcolor=#e0ffff|ORA ''abs'',Y
|
|
| bgcolor=#e0ffff|ORA ''abs'',X
| bgcolor=#e0ffff|ASL ''abs'',X
|-
! 2
| bgcolor=#e0ffff|JSR ''abs''
| bgcolor=#ffe0ff|AND (''ind'',X)
|
| bgcolor=#ffe0e0|BIT ''zpg''
| bgcolor=#ffe0e0|AND ''zpg''
| bgcolor=#ffe0e0|ROL ''zpg''
| bgcolor=#e0e0e0|PLP
| bgcolor=#e0ffe0|AND #
| bgcolor=#e0e0e0|ROL A
| bgcolor=#e0ffff|BIT ''abs''
| bgcolor=#e0ffff|AND ''abs''
| bgcolor=#e0ffff|ROL ''abs''
|-
! 3
| bgcolor=#ffffe0|BMI ''rel''
| bgcolor=#ffe0ff|AND (''ind''),Y
|
|
| bgcolor=#ffe0e0|AND ''zpg'',X
| bgcolor=#ffe0e0|ROL ''zpg'',X
| bgcolor=#e0e0e0|SEC
| bgcolor=#e0ffff|AND ''abs'',Y
|
|
| bgcolor=#e0ffff|AND ''abs'',X
| bgcolor=#e0ffff|ROL ''abs'',X
|-
! 4
| bgcolor=#e0e0e0|RTI
| bgcolor=#ffe0ff|EOR (''ind'',X)
|
|
| bgcolor=#ffe0e0|EOR ''zpg''
| bgcolor=#ffe0e0|LSR ''zpg''
| bgcolor=#e0e0e0|PHA
| bgcolor=#e0ffe0|EOR #
| bgcolor=#e0e0e0|LSR A
| bgcolor=#e0ffff|JMP ''abs''
| bgcolor=#e0ffff|EOR ''abs''
| bgcolor=#e0ffff|LSR ''abs''
|-
! 5
| bgcolor=#ffffe0|BVC ''rel''
| bgcolor=#ffe0ff|EOR (''ind''),Y
|
|
| bgcolor=#ffe0e0|EOR ''zpg'',X
| bgcolor=#ffe0e0|LSR ''zpg'',X
| bgcolor=#e0e0e0|CLI
| bgcolor=#e0ffff|EOR ''abs'',Y
|
|
| bgcolor=#e0ffff|EOR ''abs'',X
| bgcolor=#e0ffff|LSR ''abs'',X
|-
! 6
| bgcolor=#e0e0e0|RTS
| bgcolor=#ffe0ff|ADC (''ind'',X)
|
|
| bgcolor=#ffe0e0|ADC ''zpg''
| bgcolor=#ffe0e0|ROR ''zpg''
| bgcolor=#e0e0e0|PLA
| bgcolor=#e0ffe0|ADC #
| bgcolor=#e0e0e0|ROR A
| bgcolor=#ffe0ff|JMP (''ind'')
| bgcolor=#e0ffff|ADC ''abs''
| bgcolor=#e0ffff|ROR ''abs''
|-
! 7
| bgcolor=#ffffe0|BVS ''rel''
| bgcolor=#ffe0ff|ADC (''ind''),Y
|
|
| bgcolor=#ffe0e0|ADC ''zpg'',X
| bgcolor=#ffe0e0|ROR ''zpg'',X
| bgcolor=#e0e0e0|SEI
| bgcolor=#e0ffff|ADC ''abs'',Y
|
|
| bgcolor=#e0ffff|ADC ''abs'',X
| bgcolor=#e0ffff|ROR ''abs'',X
|-
! 8
|
| bgcolor=#ffe0ff|STA (''ind'',X)
|
| bgcolor=#ffe0e0|STY ''zpg''
| bgcolor=#ffe0e0|STA ''zpg''
| bgcolor=#ffe0e0|STX ''zpg''
| bgcolor=#e0e0e0|DEY
|
| bgcolor=#e0e0e0|TXA
| bgcolor=#e0ffff|STY ''abs''
| bgcolor=#e0ffff|STA ''abs''
| bgcolor=#e0ffff|STX ''abs''
|-
! 9
| bgcolor=#ffffe0|BCC ''rel''
| bgcolor=#ffe0ff|STA (''ind''),Y
|
| bgcolor=#ffe0e0|STY ''zpg'',X
| bgcolor=#ffe0e0|STA ''zpg'',X
| bgcolor=#ffe0e0|STX ''zpg'',Y
| bgcolor=#e0e0e0|TYA
| bgcolor=#e0ffff|STA ''abs'',Y
| bgcolor=#e0e0e0|TXS
|
| bgcolor=#e0ffff|STA ''abs'',X
|
|-
! A
| bgcolor=#e0ffe0|LDY #
| bgcolor=#ffe0ff|LDA (''ind'',X)
| bgcolor=#e0ffe0|LDX #
| bgcolor=#ffe0e0|LDY ''zpg''
| bgcolor=#ffe0e0|LDA ''zpg''
| bgcolor=#ffe0e0|LDX ''zpg''
| bgcolor=#e0e0e0|TAY
| bgcolor=#e0ffe0|LDA #
| bgcolor=#e0e0e0|TAX
| bgcolor=#e0ffff|LDY ''abs''
| bgcolor=#e0ffff|LDA ''abs''
| bgcolor=#e0ffff|LDX ''abs''
|-
! B
| bgcolor=#ffffe0|BCS ''rel''
| bgcolor=#ffe0ff|LDA (''ind''),Y
|
| bgcolor=#ffe0e0|LDY ''zpg'',X
| bgcolor=#ffe0e0|LDA ''zpg'',X
| bgcolor=#ffe0e0|LDX ''zpg'',Y
| bgcolor=#e0e0e0|CLV
| bgcolor=#e0ffff|LDA ''abs'',Y
| bgcolor=#e0e0e0|TSX
| bgcolor=#e0ffff|LDY ''abs'',X
| bgcolor=#e0ffff|LDA ''abs'',X
| bgcolor=#e0ffff|LDX ''abs'',Y
|-
! C
| bgcolor=#e0ffe0|CPY #
| bgcolor=#ffe0ff|CMP (''ind'',X)
|
| bgcolor=#ffe0e0|CPY ''zpg''
| bgcolor=#ffe0e0|CMP ''zpg''
| bgcolor=#ffe0e0|DEC ''zpg''
| bgcolor=#e0e0e0|INY
| bgcolor=#e0ffe0|CMP #
| bgcolor=#e0e0e0|DEX
| bgcolor=#e0ffff|CPY ''abs''
| bgcolor=#e0ffff|CMP ''abs''
| bgcolor=#e0ffff|DEC ''abs''
|-
! D
| bgcolor=#ffffe0|BNE ''rel''
| bgcolor=#ffe0ff|CMP (''ind''),Y
|
|
| bgcolor=#ffe0e0|CMP ''zpg'',X
| bgcolor=#ffe0e0|DEC ''zpg'',X
| bgcolor=#e0e0e0| CLD
| bgcolor=#e0ffff|CMP ''abs'',Y
|
|
| bgcolor=#e0ffff|CMP ''abs'',X
| bgcolor=#e0ffff|DEC ''abs'',X
|-
! E
| bgcolor=#e0ffe0|CPX #
| bgcolor=#ffe0ff|SBC (''ind'',X)
|
| bgcolor=#ffe0e0|CPX ''zpg''
| bgcolor=#ffe0e0|SBC ''zpg''
| bgcolor=#ffe0e0|INC ''zpg''
| bgcolor=#e0e0e0|INX
| bgcolor=#e0ffe0|SBC #
| bgcolor=#e0e0e0|NOP
| bgcolor=#e0ffff|CPX ''abs''
| bgcolor=#e0ffff|SBC ''abs''
| bgcolor=#e0ffff|INC ''abs''
|-
! F
| bgcolor=#ffffe0|BEQ ''rel''
| bgcolor=#ffe0ff|SBC (''ind''),Y
|
|
| bgcolor=#ffe0e0|SBC ''zpg'',X
| bgcolor=#ffe0e0|INC ''zpg'',X
| bgcolor=#e0e0e0|SED
| bgcolor=#e0ffff|SBC ''abs'',Y
|
|
| bgcolor=#e0ffff|SBC ''abs'',X
| bgcolor=#e0ffff|INC ''abs'',X
|-
|colspan=13|Blank opcodes (e.g., '''F2''') and all opcodes whose low nibbles are '''3''', '''7''', '''B''' and '''F''' are undefined in the 6502 instruction set.
|}
==Links==