addr/data bus, RESET signals.
1 SCLKI
2 UNDOC1VCC 3 UNDOC2GND
4 /ROM1 (BIOS,BAS)
5 /ROM2 (AMSDOS)
12 RA1
13 RA0
14 UNDOC1VCC 15 UNDOC2GND
16 /CAS0
17 /CAS1
33 PLLCK (CLK8, too?)
34 RDTA
35 UNDOC3 ?DATA (undocumented optional output to FDC) 36 UNDOC4 ?WINDOW (undocumented optional output to FDC)
37 RED
38 GRE
39 BLU
40 UNDOC2GND 41 UNDOC1VCC
42 /SYNC
43 CLK4
50 /ROMEN
51 /RESET
52 UNDOC2GND 53 UNDOC1VCC
54 /BRST (BUS RESET)
55 READY
64 D2
65 D3
66 UNDOC2GND 67 UNDOC1VCC
68 D4
69 D5
87 A15
88 /IOW
89 UNDOC2GND 90 UNDOC1VCC
91 /IOR
92 /PSTB (Printer Select) (Ann OR /IOW) (this is not STROBE)
Printer port 74LS273 chip is replaced by TWO chips: 74LS174 and 74LS175 (the
latter one includes strobe inversion).
UNDOC1Pin 35/UNDOC2 36 are probably VCC/GNDnot documented on schematic, but from PCB layout they can be connected to FDC by links. UNDOC3/UNDOC4 These are unknownoutput of internal FDC data separator.
== 160pin ASIC (CPC+/GX4000) ==