Difference between revisions of "External Interrupt"
(Created page with '== External Interrupt (INT Pin) == The INT signal is internally used by the CPC (triggered at 300Hz, and divided by software to get 50Hz/60Hz Video interrupts). The BIOS does co…') |
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Peripherals that do use external INTs: | Peripherals that do use external INTs: | ||
* [[Music Machine]] - accordingly to the manual: It can "disable" the internal interrupt, and replace it by external MIDI/ACIA interrupt. ''Unknown if/how it is really doing that, "disabling" the internal interrupt could be probably done only "shortcutting" the INT signal to 5V, which would be a rather aggressive solution - so maybe the manual only meant that software "ignores" the internal interrupt (?) - also, it referred to IRQ, which could eventually also mean NMI rather than INT...? - the Music Machine software isn't in the internet yet, so one can't disassemble/verify this.'' | * [[Music Machine]] - accordingly to the manual: It can "disable" the internal interrupt, and replace it by external MIDI/ACIA interrupt. ''Unknown if/how it is really doing that, "disabling" the internal interrupt could be probably done only "shortcutting" the INT signal to 5V, which would be a rather aggressive solution - so maybe the manual only meant that software "ignores" the internal interrupt (?) - also, it referred to IRQ, which could eventually also mean NMI rather than INT...? - the Music Machine software isn't in the internet yet, so one can't disassemble/verify this.'' | ||
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| + | When the Z80 acknowledges a maskable interrupt, it will disables acknowledgement of maskable interrupts. | ||
| + | It will then perform the appropiate interrupt method (as defined by IM0, IM1 or IM2). Interrupts should end with EI:RETI to re-enable maskable interrupts. | ||
| + | RETI is the special instruction recognised by Z80 compatible peripheral ICs. It is used to control the daisy-chain interrupt mechanism that they have. | ||
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| + | The CPC operating system interrupt handler briefly re-enables interrupts. It does this to effectively detect other interrupt sources. After this the external interrupt vector is jumped to (&003B). This is normally just a RET. | ||
| + | The gate-array interrupt is automatically acknowledged and cleared, so external maskable interrupts should only be cleared explicitly by the Z80 performing an I/O instruction, otherwise they would conflict with the gate-array interrupt and you would not know the source of the interrupt. | ||
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| + | SOFT968 Section 11 "Interrupts" mentions this. | ||
== See also == | == See also == | ||
* [[NMI]] - Non-maskable Interrupts (more commonly used by peripherals) | * [[NMI]] - Non-maskable Interrupts (more commonly used by peripherals) | ||
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| + | [[Category:Programming]] | ||
Latest revision as of 15:08, 17 December 2010
External Interrupt (INT Pin)
The INT signal is internally used by the CPC (triggered at 300Hz, and divided by software to get 50Hz/60Hz Video interrupts). The BIOS does contain some provisions for sharing the INT signal with external interrupts. However, most peripherals are using NMI's, which don't require to recurse conflicts with internal INTs.
Peripherals that do use external INTs:
- Music Machine - accordingly to the manual: It can "disable" the internal interrupt, and replace it by external MIDI/ACIA interrupt. Unknown if/how it is really doing that, "disabling" the internal interrupt could be probably done only "shortcutting" the INT signal to 5V, which would be a rather aggressive solution - so maybe the manual only meant that software "ignores" the internal interrupt (?) - also, it referred to IRQ, which could eventually also mean NMI rather than INT...? - the Music Machine software isn't in the internet yet, so one can't disassemble/verify this.
When the Z80 acknowledges a maskable interrupt, it will disables acknowledgement of maskable interrupts. It will then perform the appropiate interrupt method (as defined by IM0, IM1 or IM2). Interrupts should end with EI:RETI to re-enable maskable interrupts. RETI is the special instruction recognised by Z80 compatible peripheral ICs. It is used to control the daisy-chain interrupt mechanism that they have.
The CPC operating system interrupt handler briefly re-enables interrupts. It does this to effectively detect other interrupt sources. After this the external interrupt vector is jumped to (&003B). This is normally just a RET. The gate-array interrupt is automatically acknowledged and cleared, so external maskable interrupts should only be cleared explicitly by the Z80 performing an I/O instruction, otherwise they would conflict with the gate-array interrupt and you would not know the source of the interrupt.
SOFT968 Section 11 "Interrupts" mentions this.
See also
- NMI - Non-maskable Interrupts (more commonly used by peripherals)
